static void pxa_unmask_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
uint32_t icmr = __raw_readl(base + ICMR);
icmr |= 1 << IRQ_BIT(d->irq);
__raw_writel(icmr, base + ICMR);
}
static void omap_unmask_irq(unsigned int irq)
{
int bank = IRQ_BANK(irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_unmask_irq(struct irq_data *d)
{
int bank = IRQ_BANK(d->irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(d->irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
/* EOI interrupt */
static void davinci_ack_irq(unsigned int irq)
{
unsigned int mask;
mask = 1 << IRQ_BIT(irq);
if (irq > 31)
davinci_irq_writel(mask, IRQ_REG1_OFFSET);
else
davinci_irq_writel(mask, IRQ_REG0_OFFSET);
}
static int omap_wake_irq(struct irq_data *d, unsigned int enable)
{
int bank = IRQ_BANK(d->irq);
if (enable)
irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
else
irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
return 0;
}
static int omap_wake_irq(unsigned int irq, unsigned int enable)
{
int bank = IRQ_BANK(irq);
if (enable)
irq_banks[bank].wake_enable |= IRQ_BIT(irq);
else
irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
return 0;
}
/*
* Allows tuning the IRQ type and priority
*
* NOTE: There is currently no OMAP fiq handler for Linux. Read the
* mailing list threads on FIQ handlers if you are planning to
* add a FIQ handler for OMAP.
*/
static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
{
signed int bank;
unsigned long val, offset;
bank = IRQ_BANK(irq);
/* FIQ is only available on bank 0 interrupts */
fiq = bank ? 0 : (fiq & 0x1);
val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
irq_bank_writel(val, bank, offset);
}
/*!
* Set interrupt number "irq" in the AVIC as a wake-up source.
*
* @param irq interrupt source number
* @param enable enable as wake-up if equal to non-zero
* disble as wake-up if equal to zero
*
* @return This function returns 0 on success.
*/
static int mxc_set_wake_irq(unsigned int irq, unsigned int enable)
{
uint32_t *wakeup_intr;
uint32_t irq_bit;
if (irq < 32) {
wakeup_intr = &suspend_wakeup_low;
irq_bit = IRQ_BIT(irq);
} else {
wakeup_intr = &suspend_wakeup_high;
irq_bit = IRQ_BIT(irq - 32);
}
if (enable) {
*wakeup_intr |= irq_bit;
} else {
*wakeup_intr &= ~irq_bit;
}
return 0;
}
/* Disable interrupt */
static void meson_mask_irq(unsigned int irq)
{
unsigned int mask;
if (irq >= NR_IRQS)
return;
mask = 1 << IRQ_BIT(irq);
CLEAR_CBUS_REG_MASK(IRQ_MASK_REG(irq), mask);
dsb();
}
/* Clear interrupt */
static void meson_ack_irq(unsigned int irq)
{
unsigned int mask;
if (irq >= NR_IRQS)
return;
mask = 1 << IRQ_BIT(irq);
WRITE_CBUS_REG(IRQ_CLR_REG(irq), mask);
dsb();
}
static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
uint32_t controlreg, uint8_t controlidx)
{
if (FIQ_BIT(controlreg, controlidx)) {
/* deliver a FIQ */
s->fiqsrc[core] |= (uint32_t)1 << irq;
} else if (IRQ_BIT(controlreg, controlidx)) {
/* deliver an IRQ */
s->irqsrc[core] |= (uint32_t)1 << irq;
} else {
/* the interrupt is masked */
}
}
/* Enable interrupt */
static void meson_unmask_irq(unsigned int irq)
{
unsigned int mask;
if (irq >= NR_IRQS) {
return;
}
mask = 1 << IRQ_BIT(irq);
SET_CBUS_REG_MASK(IRQ_MASK_REG(irq), mask);
dsb();
}
/* Disable interrupt */
static void m2_mask_irq(struct irq_data *data)
{
unsigned int mask;
unsigned int irq;
irq = data->irq;
if (irq >= NR_IRQS)
return;
mask = 1 << IRQ_BIT(irq);
CLEAR_CBUS_REG_MASK(IRQ_MASK_REG(irq), mask);
dsb();
}
/* Clear interrupt */
static void m2_ack_irq(struct irq_data *data)
{
unsigned int mask;
unsigned int irq;
irq = data->irq;
if (irq >= NR_IRQS)
return;
mask = 1 << IRQ_BIT(irq);
WRITE_CBUS_REG(IRQ_CLR_REG(irq), mask);
dsb();
}
static void run_irqs(void)
{
int i;
unsigned long status;
status = TEST_AND_CLEAR_IRQ_STATUS(IRQS_MASK);
for (i = 1; i < NR_IRQS; i++) {
if (status & IRQ_BIT(i)) {
irq_enter();
generic_handle_irq(i);
irq_exit();
}
}
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int irq)
{
unsigned int mask;
rt_uint32_t l;
mask = 1 << IRQ_BIT(irq);
if (irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
}
/* Enable interrupt */
static void davinci_unmask_irq(unsigned int irq)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(irq);
if (irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
}
static void pxa_mask_irq(unsigned int irq)
{
_ICMR(irq) &= ~(1 << IRQ_BIT(irq));
}
static void pxa_unmask_irq(unsigned int irq)
{
_ICMR(irq) |= 1 << IRQ_BIT(irq);
}
void __init omap_init_irq(void)
{
int i, j;
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
if (cpu_is_omap310()) {
irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
}
#endif
printk("Total of %i interrupts in %i interrupt banks\n",
irq_bank_count * 32, irq_bank_count);
/* Mask and clear all interrupts */
for (i = 0; i < irq_bank_count; i++) {
irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
}
/* Clear any pending interrupts */
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
/* Enable interrupts in global mask */
if (cpu_is_omap730()) {
irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
}
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
for (j = i * 32; j < (i + 1) * 32; j++) {
int irq_trigger;
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip);
set_irq_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
}
/* Unmask level 2 handler */
if (cpu_is_omap730())
omap_unmask_irq(INT_730_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
omap_unmask_irq(INT_1610_IH2_IRQ);
}