/**
* Configure interrupt for a BAM pipe
*
*/
void bam_pipe_set_irq(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), irq_en);
}
/**
* Disable a BAM device
*
*/
void bam_exit(void *base, u32 ee)
{
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), BAM_IRQ, 0);
bam_write_reg(base, IRQ_EN, 0);
/* Disable the BAM */
bam_write_reg_field(base, CTRL, BAM_EN, 0);
}
/**
* Initialize a BAM device
*
*/
int bam_init(void *base, u32 ee,
u16 summing_threshold,
u32 irq_mask, u32 *version, u32 *num_pipes)
{
/* disable bit#11 because of HW bug */
u32 cfg_bits = 0xffffffff & ~(1 << 11);
u32 ver = 0;
SPS_DBG2("sps:%s:bam=0x%x(va).ee=%d.", __func__, (u32) base, ee);
ver = bam_read_reg_field(base, REVISION, BAM_REVISION);
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
SPS_ERR("sps:bam 0x%x(va) Invalid BAM REVISION 0x%x.\n",
(u32) base, ver);
return -ENODEV;
} else
SPS_INFO("sps:REVISION of BAM 0x%x is 0x%x.\n",
(u32) base, ver);
if (summing_threshold == 0) {
summing_threshold = 4;
SPS_ERR("sps:bam 0x%x(va) summing_threshold is zero , "
"use default 4.\n", (u32) base);
}
bam_write_reg_field(base, CTRL, BAM_SW_RST, 1);
/* No delay needed */
bam_write_reg_field(base, CTRL, BAM_SW_RST, 0);
bam_write_reg_field(base, CTRL, BAM_EN, 1);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, CTRL, CACHE_MISS_ERR_RESP_EN, 1);
bam_write_reg_field(base, CTRL, LOCAL_CLK_GATING, 1);
#endif
bam_write_reg(base, DESC_CNT_TRSHLD, summing_threshold);
bam_write_reg(base, CNFG_BITS, cfg_bits);
/*
* Enable Global BAM Interrupt - for error reasons ,
* filter with mask.
* Note: Pipes interrupts are disabled until BAM_P_IRQ_enn is set
*/
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), BAM_IRQ, 1);
bam_write_reg(base, IRQ_EN, irq_mask);
*num_pipes = bam_read_reg_field(base, NUM_PIPES, BAM_NUM_PIPES);
*version = ver;
return 0;
}
/**
* Reset the BAM pipe
*
*/
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), 0);
/* Disable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
/* Pipe Disable */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
/**
* Disable a BAM device
*
*/
void bam_exit(void *base, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).ee=%d.", __func__, (u32) base, ee);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), BAM_IRQ, 0);
bam_write_reg(base, IRQ_EN, 0);
/* Disable the BAM */
bam_write_reg_field(base, CTRL, BAM_EN, 0);
}
/**
* Reset the BAM pipe
*
*/
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), 0);
/* Disable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
/* Pipe Disable */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), 0);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
int bam_init(void *base, u32 ee,
u16 summing_threshold,
u32 irq_mask, u32 *version, u32 *num_pipes)
{
u32 cfg_bits = 0xffffffff & ~(1 << 11);
u32 ver = 0;
SPS_DBG2("sps:%s:bam=0x%x(va).ee=%d.", __func__, (u32) base, ee);
ver = bam_read_reg_field(base, REVISION, BAM_REVISION);
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
SPS_ERR("sps:bam 0x%x(va) Invalid BAM REVISION 0x%x.\n",
(u32) base, ver);
return -ENODEV;
} else
SPS_INFO("sps:REVISION of BAM 0x%x is 0x%x.\n",
(u32) base, ver);
if (summing_threshold == 0) {
summing_threshold = 4;
SPS_ERR("sps:bam 0x%x(va) summing_threshold is zero , "
"use default 4.\n", (u32) base);
}
bam_write_reg_field(base, CTRL, BAM_SW_RST, 1);
bam_write_reg_field(base, CTRL, BAM_SW_RST, 0);
bam_write_reg_field(base, CTRL, BAM_EN, 1);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, CTRL, CACHE_MISS_ERR_RESP_EN, 1);
bam_write_reg_field(base, CTRL, LOCAL_CLK_GATING, 1);
#endif
bam_write_reg(base, DESC_CNT_TRSHLD, summing_threshold);
bam_write_reg(base, CNFG_BITS, cfg_bits);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), BAM_IRQ, 1);
bam_write_reg(base, IRQ_EN, irq_mask);
*num_pipes = bam_read_reg_field(base, NUM_PIPES, BAM_NUM_PIPES);
*version = ver;
return 0;
}
/**
* Initialize a BAM pipe
*/
int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param,
u32 ee)
{
/* Reset the BAM pipe */
bam_write_reg(base, P_RST(pipe), 1);
/* No delay needed */
bam_write_reg(base, P_RST(pipe), 0);
/* Enable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1);
bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask);
bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode);
bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold);
bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE,
param->desc_size);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM,
param->stream_mode);
if (param->mode == BAM_PIPE_MODE_BAM2BAM) {
u32 peer_dest_addr = param->peer_phys_addr +
P_EVNT_REG(param->peer_pipe);
bam_write_reg(base, P_DATA_FIFO_ADDR(pipe),
param->data_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe),
P_DATA_FIFO_SIZE, param->data_size);
bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr);
SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x."
"peer_pipe=%d.\n",
(u32) base, pipe,
(u32) param->peer_phys_addr,
param->peer_pipe);
}
/* Pipe Enable - at last */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1);
return 0;
}
/**
* Configure interrupt for a BAM pipe
*
*/
void bam_pipe_set_irq(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), irq_en);
}
/**
* Initialize a BAM pipe
*/
int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param,
u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
/* Reset the BAM pipe */
bam_write_reg(base, P_RST(pipe), 1);
/* No delay needed */
bam_write_reg(base, P_RST(pipe), 0);
/* Enable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1);
bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask);
bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode);
bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold);
bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE,
param->desc_size);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM,
param->stream_mode);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP,
param->lock_group);
SPS_DBG("sps:bam=0x%x(va).pipe=%d.lock_group=%d.\n",
(u32) base, pipe, param->lock_group);
#endif
if (param->mode == BAM_PIPE_MODE_BAM2BAM) {
u32 peer_dest_addr = param->peer_phys_addr +
P_EVNT_REG(param->peer_pipe);
bam_write_reg(base, P_DATA_FIFO_ADDR(pipe),
param->data_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe),
P_DATA_FIFO_SIZE, param->data_size);
bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr);
SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x."
"peer_pipe=%d.\n",
(u32) base, pipe,
(u32) param->peer_phys_addr,
param->peer_pipe);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, P_CTRL(pipe), P_WRITE_NWD,
param->write_nwd);
SPS_DBG("sps:%s WRITE_NWD bit for this bam2bam pipe.",
param->write_nwd ? "Set" : "Do not set");
#endif
}
/* Pipe Enable - at last */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1);
return 0;
}
