/*
========================================================================
Routine Description:
Initialize normal beacon frame architecture.
Arguments:
pAd - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
VOID RtmpChipBcnInit(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
pChipCap->FlgIsSupSpecBcnBuf = FALSE;
pChipCap->BcnMaxHwNum = 8;
pChipCap->BcnMaxNum = (pChipCap->BcnMaxHwNum - MAX_MESH_NUM - MAX_APCLI_NUM);
pChipCap->BcnMaxHwSize = 0x1000;
#ifdef MT7601
if ( IS_MT7601(pAd))
{
pChipCap->BcnBase[0] = 0xC000;
pChipCap->BcnBase[1] = 0xC200;
pChipCap->BcnBase[2] = 0xC400;
pChipCap->BcnBase[3] = 0xC600;
pChipCap->BcnBase[4] = 0xC800;
pChipCap->BcnBase[5] = 0xCA00;
pChipCap->BcnBase[6] = 0xCC00;
pChipCap->BcnBase[7] = 0xCE00;
} else
#endif /* MT7601 */
{
pChipCap->BcnBase[0] = 0x7800;
pChipCap->BcnBase[1] = 0x7A00;
pChipCap->BcnBase[2] = 0x7C00;
pChipCap->BcnBase[3] = 0x7E00;
pChipCap->BcnBase[4] = 0x7200;
pChipCap->BcnBase[5] = 0x7400;
pChipCap->BcnBase[6] = 0x5DC0;
pChipCap->BcnBase[7] = 0x5BC0;
}
/*
If the MAX_MBSSID_NUM is larger than 6,
it shall reserve some WCID space(wcid 222~253) for beacon frames.
- these wcid 238~253 are reserved for beacon#6(ra6).
- these wcid 222~237 are reserved for beacon#7(ra7).
*/
#ifdef MT7601
if ( IS_MT7601(pAd))
pChipCap->WcidHwRsvNum = 127;
else
#endif
if (pChipCap->BcnMaxNum == 8)
pChipCap->WcidHwRsvNum = 222;
else if (pChipCap->BcnMaxNum == 7)
pChipCap->WcidHwRsvNum = 238;
else
pChipCap->WcidHwRsvNum = 255;
pAd->chipOps.BeaconUpdate = RtmpChipWriteMemory;
}
/* To stop the frequency calibration algorithm*/
VOID StopFrequencyCalibration(IN PRTMP_ADAPTER pAd)
{
if (pAd->FreqCalibrationCtrl.bEnableFrequencyCalibration == TRUE) {
DBGPRINT(RT_DEBUG_TRACE, ("---> %s\n", __FUNCTION__));
/* Base on the frequency offset of the EEPROM */
#ifdef MT7601
if (IS_MT7601(pAd))
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = pAd->RfFreqOffset; /* AdaptiveFreqOffset= RF_R12[7:0] */
else
#endif /* MT7601 */
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = (0x7F & ((CHAR) (pAd->RfFreqOffset))); /* C1 value control - Crystal calibration */
pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon =
INVALID_FREQUENCY_OFFSET;
pAd->FreqCalibrationCtrl.bSkipFirstFrequencyCalibration = TRUE;
DBGPRINT(RT_DEBUG_TRACE,
("%s: pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = 0x%X\n",
__FUNCTION__,
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset));
DBGPRINT(RT_DEBUG_TRACE, ("<--- %s\n", __FUNCTION__));
}
}
VOID RT28xxUsbStaAsicForceWakeup(
IN PRTMP_ADAPTER pAd,
IN BOOLEAN bFromTx)
{
BOOLEAN Canceled;
if (pAd->Mlme.AutoWakeupTimerRunning)
{
if ( !OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) )
{
return;
}
RTMPCancelTimer(&pAd->Mlme.AutoWakeupTimer, &Canceled);
pAd->Mlme.AutoWakeupTimerRunning = FALSE;
}
#ifdef MT7601
if ( IS_MT7601(pAd) )
{
ASIC_RADIO_ON(pAd, DOT11_RADIO_ON);
}
else
#endif /* MT7601 */
{
AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02, FALSE);
}
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
}
void RTMPGetLEDSetting(IN RTMP_ADAPTER *pAd)
{
USHORT Value;
PLED_CONTROL pLedCntl = &pAd->LedCntl;
#ifdef RT65xx
if (IS_RT6590(pAd))
{
; // TODO: wait TC6008 EEPROM format
}
else
#endif /* RT65xx */
#ifdef MT7601
if (IS_MT7601(pAd))
{
; // TODO: wait TC6008 EEPROM format
}
else
#endif /* MT7601 */
{
RT28xx_EEPROM_READ16(pAd, EEPROM_FREQ_OFFSET, Value);
pLedCntl->MCULedCntl.word = (Value >> 8);
RT28xx_EEPROM_READ16(pAd, EEPROM_LEDAG_CONF_OFFSET, Value);
pLedCntl->LedAGCfg= Value;
RT28xx_EEPROM_READ16(pAd, EEPROM_LEDACT_CONF_OFFSET, Value);
pLedCntl->LedACTCfg = Value;
RT28xx_EEPROM_READ16(pAd, EEPROM_LED_POLARITY_OFFSET, Value);
pLedCntl->LedPolarity = Value;
}
}
int get_pkt_snr_by_rxwi(struct _RTMP_ADAPTER *pAd, RXWI_STRUC *rxwi, int size, UCHAR *snr)
{
#ifdef MT7601
/*
snr[2] = Gain Report
snr[1] = Antenna report
*/
if ( IS_MT7601(pAd) )
{
snr[0] = rxwi->RxWISNR0;
snr[1] = 0;
snr[2] = 0;
return 0;
}
#endif /* MT7601 */
switch (size) {
case 3:
snr[2] = rxwi->RxWISNR2;
case 2:
snr[1] = rxwi->RxWISNR1;
case 1:
default:
snr[0] = rxwi->RxWISNR0;
break;
}
return 0;
}
/*
========================================================================
Routine Description:
Initialize specific beacon frame architecture.
Arguments:
pAd - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
VOID rlt_bcn_buf_init(RTMP_ADAPTER *pAd)
{
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
pChipCap->FlgIsSupSpecBcnBuf = FALSE;
#if defined(MT7601) || defined(MT76x2)
if (IS_MT7601(pAd) || IS_MT76x2(pAd))
{
pChipCap->BcnMaxHwNum = 8;
pChipCap->WcidHwRsvNum = 127;
}
else
#endif /* MT7601 || MT76x2 */
{
pChipCap->BcnMaxHwNum = 16;
pChipCap->WcidHwRsvNum = 255;
}
/*
In 16-MBSS support mode, if AP-Client is enabled,
the last 8-MBSS would be occupied for AP-Client using.
*/
#ifdef APCLI_SUPPORT
pChipCap->BcnMaxNum = (8 - MAX_MESH_NUM);
#else
pChipCap->BcnMaxNum = (pChipCap->BcnMaxHwNum - MAX_MESH_NUM);
#endif /* APCLI_SUPPORT */
pChipCap->BcnMaxHwSize = 0x2000;
pChipCap->BcnBase[0] = 0xc000;
pChipCap->BcnBase[1] = 0xc200;
pChipCap->BcnBase[2] = 0xc400;
pChipCap->BcnBase[3] = 0xc600;
pChipCap->BcnBase[4] = 0xc800;
pChipCap->BcnBase[5] = 0xca00;
pChipCap->BcnBase[6] = 0xcc00;
pChipCap->BcnBase[7] = 0xce00;
pChipCap->BcnBase[8] = 0xd000;
pChipCap->BcnBase[9] = 0xd200;
pChipCap->BcnBase[10] = 0xd400;
pChipCap->BcnBase[11] = 0xd600;
pChipCap->BcnBase[12] = 0xd800;
pChipCap->BcnBase[13] = 0xda00;
pChipCap->BcnBase[14] = 0xdc00;
pChipCap->BcnBase[15] = 0xde00;
#ifdef CONFIG_MULTI_CHANNEL
/* Record HW Null Frame offset */
//pAd->NullBufOffset[0] = 0xd000;
pAd->NullBufOffset[0] = 0xd000;
pAd->NullBufOffset[1] = 0xd200;
#endif /* CONFIG_MULTI_CHANNEL */
pAd->chipOps.BeaconUpdate = RtmpChipWriteMemory;
}
VOID RT28xxUsbStaAsicSleepThenAutoWakeup(
IN PRTMP_ADAPTER pAd,
IN USHORT TbttNumToNextWakeUp)
{
/* Not going to sleep if in the Count Down Time*/
if (pAd->CountDowntoPsm > 0)
return;
if (pAd->Mlme.AutoWakeupTimerRunning == TRUE)
return;
/* we have decided to SLEEP, so at least do it for a BEACON period.*/
if (TbttNumToNextWakeUp == 0)
TbttNumToNextWakeUp = 1;
RTMPSetTimer(&pAd->Mlme.AutoWakeupTimer, AUTO_WAKEUP_TIMEOUT);
pAd->Mlme.AutoWakeupTimerRunning = TRUE;
#ifdef MT7601
if ( IS_MT7601(pAd) )
{
ASIC_RADIO_OFF(pAd, DOT11_RADIO_OFF);
}
else
#endif /* MT7601 */
{
AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02, FALSE); /* send POWER-SAVE command to MCU. Timeout 40us.*/
/* cancel bulk-in IRPs prevent blocking CPU enter C3.*/
if((pAd->PendingRx > 0) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
RTUSBCancelPendingBulkInIRP(pAd);
/* resend bulk-in IRPs to receive beacons after a period of (pAd->CommonCfg.BeaconPeriod - 40) ms*/
pAd->PendingRx = 0;
}
}
OPSTATUS_SET_FLAG(pAd, fOP_STATUS_DOZE);
}
int get_pkt_rssi_by_rxwi(struct _RTMP_ADAPTER *pAd, RXWI_STRUC *rxwi, int size, CHAR *rssi)
{
switch (size) {
case 3:
rssi[2] = rxwi->RxWIRSSI2;
case 2:
rssi[1] = rxwi->RxWIRSSI1;
case 1:
default:
#ifdef MT7601
if ( IS_MT7601(pAd) )
rssi[0] = rxwi->RxWISNR2;
else
#endif /* MT7601 */
rssi[0] = rxwi->RxWIRSSI0;
break;
}
return 0;
}
VOID RtmpUsbStaAsicForceWakeupTimeout(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
IN PVOID SystemSpecific2,
IN PVOID SystemSpecific3)
{
RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)FunctionContext;
if (pAd && pAd->Mlme.AutoWakeupTimerRunning)
{
#ifdef MT7601
if ( IS_MT7601(pAd) )
{
if ( !OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) )
{
RTMPSetTimer(&pAd->Mlme.AutoWakeupTimer, AUTO_WAKEUP_TIMEOUT);
return;
}
ASIC_RADIO_ON(pAd, MLME_RADIO_ON);
}
else
#endif /* MT7601 */
{
RTUSBBulkReceive(pAd);
AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02, FALSE);
}
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
pAd->Mlme.AutoWakeupTimerRunning = FALSE;
}
}
static INT rtmp_bbp_init(RTMP_ADAPTER *pAd)
{
INT Index = 0;
/* Read BBP register, make sure BBP is up and running before write new data*/
if (rtmp_bbp_is_ready(pAd)== FALSE)
return FALSE;
Index = 0;
/* Initialize BBP register to default value*/
for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
{
#ifdef RTMP_RBUS_SUPPORT
if (pAd->infType == RTMP_DEV_INF_RBUS)
{
if (Index == BBP_R105)
{
/*
kurtis:0x01 ori 0x05 is for rt2860E to turn on FEQ control.
It is safe for rt2860D and before, because Bit 7:2
are reserved in rt2860D and before.
*/
BBPRegTable[Index].Value=0x01;
DBGPRINT(RT_DEBUG_TRACE,
("RBUS:BBP[%d] = %x\n",(INT)Index,
BBPRegTable[Index].Value));
}
}
#endif /* RTMP_RBUS_SUPPORT */
#ifdef MICROWAVE_OVEN_SUPPORT
#endif /* MICROWAVE_OVEN_SUPPORT */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
BBPRegTable[Index].Register,
BBPRegTable[Index].Value);
}
/* re-config specific BBP registers for individual chip */
if (pAd->chipCap.pBBPRegTable)
{
REG_PAIR *reg_list = pAd->chipCap.pBBPRegTable;
for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
reg_list[Index].Register,
reg_list[Index].Value);
DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n",
reg_list[Index].Register,
reg_list[Index].Value));
}
}
if (pAd->chipOps.AsicBbpInit != NULL)
pAd->chipOps.AsicBbpInit(pAd);
/*
For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
3070/71/72,3090,3090A( are included in RT30xx),3572,3390
*/
if (((pAd->MACVersion & 0xffff) != 0x0101) &&
!(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd) || IS_RT6352(pAd) || IS_MT76x2(pAd)))
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
}
return TRUE;
}
/* The frequency calibration algorithm*/
VOID FrequencyCalibration(IN PRTMP_ADAPTER pAd)
{
/*BOOLEAN bUpdateRFR = FALSE; */
CHAR HighFreqTriggerPoint = 0, LowFreqTriggerPoint = 0;
CHAR DecreaseFreqOffset = 0, IncreaseFreqOffset = 0;
/* Frequency calibration period: */
/* a) 10 seconds: Check the reported frequency offset */
/* b) 500 ms: Update the RF frequency if possible */
if ((pAd->FreqCalibrationCtrl.bEnableFrequencyCalibration == TRUE) &&
(((pAd->FreqCalibrationCtrl.bApproachFrequency == FALSE)
&& ((pAd->Mlme.PeriodicRound % FREQUENCY_CALIBRATION_PERIOD) ==
0)) || ((pAd->FreqCalibrationCtrl.bApproachFrequency == TRUE)
&&
((pAd->Mlme.PeriodicRound %
(FREQUENCY_CALIBRATION_PERIOD / 20)) == 0)))) {
DBGPRINT(RT_DEBUG_INFO, ("---> %s\n", __FUNCTION__));
if (pAd->FreqCalibrationCtrl.bSkipFirstFrequencyCalibration ==
TRUE) {
pAd->
FreqCalibrationCtrl.bSkipFirstFrequencyCalibration =
FALSE;
DBGPRINT(RT_DEBUG_INFO,
("%s: Skip cuurent frequency calibration (avoid calibrating frequency at the time the STA is just link-up)\n",
__FUNCTION__));
} else {
if (pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon !=
INVALID_FREQUENCY_OFFSET) {
/* Sync the thresholds */
if (pAd->FreqCalibrationCtrl.BeaconPhyMode == MODE_CCK) { /* CCK */
#ifdef MT7601
if (IS_MT7601(pAd)) {
HighFreqTriggerPoint =
MT7601_HIGH_FREQUENCY_TRIGGER_POINT_CCK;
LowFreqTriggerPoint =
MT7601_LOW_FREQUENCY_TRIGGER_POINT_CCK;
DecreaseFreqOffset =
MT7601_DECREASE_FREQUENCY_OFFSET_CCK;
IncreaseFreqOffset =
MT7601_INCREASE_FREQUENCY_OFFSET_CCK;
} else
#endif /* MT7601 */
{
HighFreqTriggerPoint =
HIGH_FREQUENCY_TRIGGER_POINT_CCK;
LowFreqTriggerPoint =
LOW_FREQUENCY_TRIGGER_POINT_CCK;
DecreaseFreqOffset =
DECREASE_FREQUENCY_OFFSET_CCK;
IncreaseFreqOffset =
INCREASE_FREQUENCY_OFFSET_CCK;
}
} else { /* OFDM */
#ifdef MT7601
if (IS_MT7601(pAd)) {
DBGPRINT(RT_DEBUG_ERROR,
("%s:MT7601 receive OFDM beacon.\n",
__FUNCTION__));
HighFreqTriggerPoint =
MT7601_HIGH_FREQUENCY_TRIGGER_POINT_OFDM20;
LowFreqTriggerPoint =
MT7601_LOW_FREQUENCY_TRIGGER_POINT_OFDM20;
DecreaseFreqOffset =
MT7601_DECREASE_FREQUENCY_OFFSET_OFDM20;
IncreaseFreqOffset =
MT7601_INCREASE_FREQUENCY_OFFSET_OFDM20;
} else
#endif /* MT7601 */
{
HighFreqTriggerPoint =
HIGH_FREQUENCY_TRIGGER_POINT_OFDM;
LowFreqTriggerPoint =
LOW_FREQUENCY_TRIGGER_POINT_OFDM;
DecreaseFreqOffset =
DECREASE_FREQUENCY_OFFSET_OFDM;
IncreaseFreqOffset =
INCREASE_FREQUENCY_OFFSET_OFDM;
}
}
if ((pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
>= HighFreqTriggerPoint)
|| (pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
<= LowFreqTriggerPoint)) {
pAd->
FreqCalibrationCtrl.bApproachFrequency
= TRUE;
}
if (pAd->
FreqCalibrationCtrl.bApproachFrequency ==
TRUE) {
if ((pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
<= DecreaseFreqOffset)
&& (pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
>= IncreaseFreqOffset)) {
pAd->FreqCalibrationCtrl.bApproachFrequency = FALSE; /* Stop approaching frquency if -10 < reported frequency offset < 10 */
} else if (pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
> DecreaseFreqOffset) {
#ifdef MT7601
if (pAd->
FreqCalibrationCtrl.AdaptiveFreqOffset
> 0)
#endif /* MT7601 */
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset--;
DBGPRINT(RT_DEBUG_TRACE,
("%s: -- frequency offset = 0x%X\n",
__FUNCTION__,
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset));
FrequencyCalibrationMode(pAd,
pAd->chipCap.FreqCalMode);
} else if (pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon
< IncreaseFreqOffset) {
#ifdef MT7601
if (pAd->
FreqCalibrationCtrl.AdaptiveFreqOffset
< 0xBF)
#endif /* MT7601 */
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset++;
DBGPRINT(RT_DEBUG_TRACE,
("%s: ++ frequency offset = 0x%X\n",
__FUNCTION__,
pAd->FreqCalibrationCtrl.AdaptiveFreqOffset));
FrequencyCalibrationMode(pAd,
pAd->chipCap.FreqCalMode);
}
}
DBGPRINT(RT_DEBUG_INFO,
("%s: AdaptiveFreqOffset = %d, LatestFreqOffsetOverBeacon = %d, bApproachFrequency = %d\n",
__FUNCTION__,
pAd->
FreqCalibrationCtrl.AdaptiveFreqOffset,
pAd->
FreqCalibrationCtrl.LatestFreqOffsetOverBeacon,
pAd->
FreqCalibrationCtrl.bApproachFrequency));
}
}
DBGPRINT(RT_DEBUG_INFO, ("<--- %s\n", __FUNCTION__));
}
}
/*
========================================================================
Routine Description:
Calculates the duration which is required to transmit out frames
with given size and specified rate.
Arguments:
pTxWI Pointer to head of each MPDU to HW.
Ack Setting for Ack requirement bit
Fragment Setting for Fragment bit
RetryMode Setting for retry mode
Ifs Setting for IFS gap
Rate Setting for transmit rate
Service Setting for service
Length Frame length
TxPreamble Short or Long preamble when using CCK rates
QueIdx - 0-3, according to 802.11e/d4.4 June/2003
Return Value:
None
See also : BASmartHardTransmit() !!!
========================================================================
*/
VOID RTMPWriteTxWI(
IN RTMP_ADAPTER *pAd,
IN TXWI_STRUC *pOutTxWI,
IN BOOLEAN FRAG,
IN BOOLEAN CFACK,
IN BOOLEAN InsTimestamp,
IN BOOLEAN AMPDU,
IN BOOLEAN Ack,
IN BOOLEAN NSeq, /* HW new a sequence.*/
IN UCHAR BASize,
IN UCHAR WCID,
IN ULONG Length,
IN UCHAR PID,
IN UCHAR TID,
IN UCHAR TxRate,
IN UCHAR Txopmode,
IN BOOLEAN CfAck,
IN HTTRANSMIT_SETTING *pTransmit)
{
PMAC_TABLE_ENTRY pMac = NULL;
TXWI_STRUC TxWI, *pTxWI;
UINT8 TXWISize = pAd->chipCap.TXWISize;
if (WCID < MAX_LEN_OF_MAC_TABLE)
pMac = &pAd->MacTab.Content[WCID];
/*
Always use Long preamble before verifiation short preamble functionality works well.
Todo: remove the following line if short preamble functionality works
*/
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
NdisZeroMemory(&TxWI, TXWISize);
pTxWI = &TxWI;
pTxWI->TxWIFRAG= FRAG;
pTxWI->TxWICFACK = CFACK;
pTxWI->TxWITS= InsTimestamp;
pTxWI->TxWIAMPDU = AMPDU;
pTxWI->TxWIACK = Ack;
pTxWI->TxWITXOP= Txopmode;
pTxWI->TxWINSEQ = NSeq;
/* John tune the performace with Intel Client in 20 MHz performance*/
#ifdef DOT11_N_SUPPORT
BASize = pAd->CommonCfg.TxBASize;
#ifdef RT65xx
if (IS_RT65XX(pAd))
{
if (BASize > 31)
BASize =31;
}
else
#endif /* RT65xx */
#ifdef MT7601
if (IS_MT7601(pAd))
{
if (BASize > 15)
BASize =15;
}
else
#endif /* MT7601 */
if (pAd->MACVersion == 0x28720200)
{
if (BASize > 13)
BASize =13;
}
else
{
if( BASize >7 )
BASize =7;
}
pTxWI->TxWIBAWinSize = BASize;
pTxWI->TxWIShortGI = pTransmit->field.ShortGI;
pTxWI->TxWISTBC = pTransmit->field.STBC;
#ifdef TXBF_SUPPORT
if (pMac && pAd->chipCap.FlgHwTxBfCap)
{
if (pMac->TxSndgType == SNDG_TYPE_NDP || pMac->TxSndgType == SNDG_TYPE_SOUNDING || pTxWI->eTxBF)
pTxWI->TxWISTBC = 0;
}
#endif /* TXBF_SUPPORT */
#endif /* DOT11_N_SUPPORT */
pTxWI->TxWIWirelessCliID = WCID;
pTxWI->TxWIMPDUByteCnt = Length;
#ifdef RLT_MAC
pTxWI->TxWIPacketId = PID;
#endif /* RLT_MAC */
/* If CCK or OFDM, BW must be 20*/
pTxWI->TxWIBW = (pTransmit->field.MODE <= MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
#ifdef DOT11_N_SUPPORT
#ifdef DOT11N_DRAFT3
if (pTxWI->TxWIBW)
pTxWI->TxWIBW = (pAd->CommonCfg.AddHTInfo.AddHtInfo.RecomWidth == 0) ? (BW_20) : (pTransmit->field.BW);
#endif /* DOT11N_DRAFT3 */
#endif /* DOT11_N_SUPPORT */
pTxWI->TxWIMCS = pTransmit->field.MCS;
pTxWI->TxWIPHYMODE = pTransmit->field.MODE;
pTxWI->TxWICFACK = CfAck;
#ifdef DOT11_N_SUPPORT
if (pMac)
{
if (pAd->CommonCfg.bMIMOPSEnable)
{
if ((pMac->MmpsMode == MMPS_DYNAMIC) && (pTransmit->field.MCS > 7))
{
/* Dynamic MIMO Power Save Mode*/
pTxWI->TxWIMIMOps = 1;
}
else if (pMac->MmpsMode == MMPS_STATIC)
{
/* Static MIMO Power Save Mode*/
if (pTransmit->field.MODE >= MODE_HTMIX && pTransmit->field.MCS > 7)
{
pTxWI->TxWIMCS = 7;
pTxWI->TxWIMIMOps = 0;
}
}
}
/*pTxWI->TxWIMIMOps = (pMac->PsMode == PWR_MMPS)? 1:0;*/
{
pTxWI->TxWIMpduDensity = pMac->MpduDensity;
}
}
#endif /* DOT11_N_SUPPORT */
#ifdef RLT_MAC
pTxWI->TxWIPacketId = pTxWI->TxWIMCS;
#endif /* RLT_MAC */
NdisMoveMemory(pOutTxWI, &TxWI, TXWISize);
//+++Add by shiang for debug
if (0){
hex_dump("TxWI", (UCHAR *)pOutTxWI, TXWISize);
}
//---Add by shiang for debug
}
/*
========================================================================
Routine Description:
Initialize chip related information.
Arguments:
pCB - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
VOID RtmpChipOpsHook(VOID *pCB)
{
RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)pCB;
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
UINT32 MacValue;
/* sanity check */
WaitForAsicReady(pAd);
RTMP_IO_READ32(pAd, MAC_CSR0, &MacValue);
pAd->MACVersion = MacValue;
/* default init */
RTMP_DRS_ALG_INIT(pAd, RATE_ALG_LEGACY);
#ifdef RT3290
if (IS_RT3290(pAd))
{
RT3290_Init(pAd);
goto done;
}
#endif /* RT290 */
#ifdef RT8592
if (IS_RT8592(pAd)) {
RT85592_Init(pAd);
goto done;
}
#endif /* RT8592 */
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
RT6590_Init(pAd);
goto done;
}
#endif /* RT65xx */
#ifdef MT7601
if (IS_MT7601(pAd)) {
MT7601_Init(pAd);
goto done;
}
#endif /* MT7601 */
/* init default value whatever chipsets */
/* default pChipOps content will be 0x00 */
pChipCap->bbpRegTbSize = 0;
pChipCap->MaxNumOfRfId = 31;
pChipCap->MaxNumOfBbpId = 136;
pChipCap->SnrFormula = SNR_FORMULA1;
pChipCap->RfReg17WtMethod = RF_REG_WT_METHOD_NONE;
pChipCap->TXWISize = 16;
pChipCap->RXWISize = 16;
#if defined(RTMP_INTERNAL_TX_ALC) || defined(RTMP_TEMPERATURE_COMPENSATION)
pChipCap->TxPowerTuningTable_2G = TxPowerTuningTableOrg;
#ifdef A_BAND_SUPPORT
pChipCap->TxPowerTuningTable_5G = TxPowerTuningTableOrg;
#endif /* A_BAND_SUPPORT */
#endif /* defined(RTMP_INTERNAL_TX_ALC) || defined(RTMP_TEMPERATURE_COMPENSATION) */
pChipOps->AsicMacInit = NULL;
pChipOps->AsicBbpInit = NULL;
pChipOps->AsicRfInit = NULL;
#ifdef RTMP_EFUSE_SUPPORT
pChipCap->EFUSE_USAGE_MAP_START = 0x2d0;
pChipCap->EFUSE_USAGE_MAP_END = 0x2fc;
pChipCap->EFUSE_USAGE_MAP_SIZE = 45;
#endif /* RTMP_EFUSE_SUPPORT */
pChipCap->VcoPeriod = 10;
pChipCap->FlgIsVcoReCalMode = VCO_CAL_DISABLE;
pChipCap->WPDMABurstSIZE = 2; /* default 64B */
pChipCap->MBSSIDMode = MBSSID_MODE0;
RtmpChipBcnInit(pAd);
pChipOps->RxSensitivityTuning = RxSensitivityTuning;
#ifdef CONFIG_STA_SUPPORT
pChipOps->ChipAGCAdjust = ChipAGCAdjust;
#endif /* CONFIG_STA_SUPPORT */
pChipOps->ChipBBPAdjust = ChipBBPAdjust;
pChipOps->ChipSwitchChannel = Default_ChipSwitchChannel;
/* TX ALC */
pChipCap->bTempCompTxALC = FALSE;
pChipOps->AsicGetTxPowerOffset = NULL;
pChipOps->InitDesiredTSSITable = NULL;
pChipOps->AsicTxAlcGetAutoAgcOffset = NULL;
pChipOps->AsicExtraPowerOverMAC = NULL;
pChipOps->ChipAGCInit = Default_ChipAGCInit;
pChipOps->AsicAntennaDefaultReset = AsicAntennaDefaultReset;
pChipOps->NetDevNickNameInit = NetDevNickNameInit;
/* Init value. If pChipOps->AsicResetBbpAgent==NULL, "AsicResetBbpAgent" as default. If your chipset has specific routine, please re-hook it at self init function */
pChipOps->AsicResetBbpAgent = NULL;
pChipOps->InitTemperCompensation = NULL;
pChipOps->TemperCompensation = NULL;
#ifdef RT28xx
pChipOps->ChipSwitchChannel = RT28xx_ChipSwitchChannel;
#endif /* RT28xx */
#ifdef CARRIER_DETECTION_SUPPORT
pChipCap->carrier_func = DISABLE_TONE_RADAR;
pChipOps->ToneRadarProgram = NULL;
#endif /* CARRIER_DETECTOIN_SUPPORT */
#ifdef DFS_SUPPORT
pChipCap->DfsEngineNum = 4;
#endif /* DFS_SUPPORT */
pChipOps->CckMrcStatusCtrl = NULL;
pChipOps->RadarGLRTCompensate = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#if defined(RT3883) || defined(RT3290) || defined(RT65xx) || defined(MT7601)
done:
#endif /* defined(RT3883) || defined(RT3290) || defined(RT65xx) || define(MT7601) */
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipCap->bbpRegTbSize));
DBGPRINT(RT_DEBUG_TRACE, ("Chip VCO calibration mode = %d!\n", pChipCap->FlgIsVcoReCalMode));
}
NDIS_STATUS NICInitBBP(RTMP_ADAPTER *pAd)
{
INT Index = 0;
/* Read BBP register, make sure BBP is up and running before write new data*/
if (rtmp_bbp_is_ready(pAd)== FALSE)
return NDIS_STATUS_FAILURE;
Index = 0;
/* Initialize BBP register to default value*/
for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
{
#ifdef MICROWAVE_OVEN_SUPPORT
#ifdef MT7601
if ( BBPRegTable[Index].Register == BBP_R65)
{
/* Backup BBP_R65 and B5.R6 and B5.R7 */
pAd->CommonCfg.MO_Cfg.Stored_BBP_R65 = BBPRegTable[Index].Value;
DBGPRINT(RT_DEBUG_TRACE, ("Stored_BBP_R65=%x @%s \n", pAd->CommonCfg.MO_Cfg.Stored_BBP_R65, __FUNCTION__));
}
#endif /* MT7601 */
#endif /* MICROWAVE_OVEN_SUPPORT */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
BBPRegTable[Index].Register,
BBPRegTable[Index].Value);
}
/* re-config specific BBP registers for individual chip */
if (pAd->chipCap.pBBPRegTable)
{
REG_PAIR *pbbpRegTb = pAd->chipCap.pBBPRegTable;
for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
pbbpRegTb[Index].Register,
pbbpRegTb[Index].Value);
DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n",
pbbpRegTb[Index].Register,
pbbpRegTb[Index].Value));
}
}
if (pAd->chipOps.AsicBbpInit != NULL)
pAd->chipOps.AsicBbpInit(pAd);
/*
For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
3070/71/72,3090,3090A( are included in RT30xx),3572,3390
*/
if (((pAd->MACVersion & 0xffff) != 0x0101) &&
!(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd)))
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
}
return NDIS_STATUS_SUCCESS;
}
void STA_MonPktSend(
IN RTMP_ADAPTER *pAd,
IN RX_BLK *pRxBlk)
{
PNET_DEV pNetDev;
PNDIS_PACKET pRxPacket;
PHEADER_802_11 pHeader;
USHORT DataSize;
UINT32 MaxRssi;
UCHAR L2PAD, PHYMODE, BW, ShortGI, MCS, AMPDU, STBC, RSSI1;
UCHAR BssMonitorFlag11n, Channel, CentralChannel;
UCHAR *pData, *pDevName;
/* sanity check */
ASSERT(pRxBlk->pRxPacket);
if (pRxBlk->DataSize < 10)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too small! (%d)\n", __FUNCTION__, pRxBlk->DataSize));
goto err_free_sk_buff;
}
if (pRxBlk->DataSize + sizeof(wlan_ng_prism2_header) > RX_BUFFER_AGGRESIZE)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s : Size is too large! (%d)\n", __FUNCTION__, pRxBlk->DataSize + (UINT)sizeof(wlan_ng_prism2_header)));
goto err_free_sk_buff;
}
/* init */
#ifdef MT7601
if ( IS_MT7601(pAd) )
MaxRssi = ConvertToRssi(pAd, pRxBlk->pRxWI->RxWISNR2, RSSI_0, pRxBlk->pRxWI->RxWISNR1, pRxBlk->pRxWI->RxWIBW);
else
#endif /* MT7601 */
MaxRssi = RTMPMaxRssi(pAd,
ConvertToRssi(pAd, pRxBlk->pRxWI->RxWIRSSI0, RSSI_0, 0, 0),
ConvertToRssi(pAd, pRxBlk->pRxWI->RxWIRSSI1, RSSI_1, 0, 0),
ConvertToRssi(pAd, pRxBlk->pRxWI->RxWIRSSI2, RSSI_2, 0, 0));
pNetDev = get_netdev_from_bssid(pAd, BSS0);
pRxPacket = pRxBlk->pRxPacket;
pHeader = pRxBlk->pHeader;
pData = pRxBlk->pData;
DataSize = pRxBlk->DataSize;
L2PAD = pRxBlk->pRxInfo->L2PAD;
PHYMODE = pRxBlk->pRxWI->RxWIPhyMode;
BW = pRxBlk->pRxWI->RxWIBW;
ShortGI = pRxBlk->pRxWI->RxWISGI;
MCS = pRxBlk->pRxWI->RxWIMCS;
AMPDU = pRxBlk->pRxInfo->AMPDU;
STBC = pRxBlk->pRxWI->RxWISTBC;
RSSI1 = pRxBlk->pRxWI->RxWIRSSI1;
BssMonitorFlag11n = 0;
#ifdef MONITOR_FLAG_11N_SNIFFER_SUPPORT
BssMonitorFlag11n = (pAd->StaCfg.BssMonitorFlag & MONITOR_FLAG_11N_SNIFFER);
#endif /* MONITOR_FLAG_11N_SNIFFER_SUPPORT */
pDevName = (UCHAR *)RtmpOsGetNetDevName(pAd->net_dev);
Channel = pAd->CommonCfg.Channel;
CentralChannel = pAd->CommonCfg.CentralChannel;
/* pass the packet */
send_monitor_packets(pNetDev, pRxPacket, pHeader, pData, DataSize,
L2PAD, PHYMODE, BW, ShortGI, MCS, AMPDU, STBC, RSSI1,
BssMonitorFlag11n, pDevName, Channel, CentralChannel,
MaxRssi);
return;
err_free_sk_buff:
RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket, NDIS_STATUS_FAILURE);
return;
}
