Exemplo n.º 1
0
static void WriteInitialRegisterValues(void)
{
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x08, 0x37);

	I2C_WriteByte(TPI_SLAVE_ADDR, 0xA0, 0xD0);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0xA1, 0xFC);

	I2C_WriteByte(TPI_SLAVE_ADDR, 0xA3, 0xC0);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0xA6, 0x0C);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x2B, 0x01);

	ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_2);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x91, 0xA5);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x94, 0x75);


	I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);

	I2C_WriteByte(TPI_SLAVE_ADDR, 0xA5, 0xA0);
	TPI_DEBUG_PRINT(("1x Mode\n"));
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x95, 0x31);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x96, 0x20);

	ReadModifyWriteTPI(0x97,  BIT_1, 0);

	ReadModifyWriteTPI(0x95, BIT_6, BIT_6);
	WriteByteTPI(0x92, 0x86);
	WriteByteTPI(0x93, 0xCC);
	if (txPowerState != TX_POWER_STATE_D3) {
		ReadModifyWriteTPI(0x79, BIT_5 | BIT_4, BIT_4);
	}

	DelayMS(25);
	ReadModifyWriteTPI(0x95, BIT_6, 0x00);
	ReadModifyWriteTPI(0x78, BIT_5, 0);

	I2C_WriteByte(TPI_SLAVE_ADDR, 0x90, 0x27);

	I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x08);
	DelayMS(2);
	I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x00);

	InitCBusRegs();

	I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, ASR_VALUE);
	}
Exemplo n.º 2
0
static void WriteInitialRegisterValues ( void )
{
	TX_DEBUG_PRINT(("WriteInitialRegisterValues\n"));
	SiiRegWrite(REG_POWER_EN, 0x3F);			
	SiiRegWrite(REG_MHLTX_CTL6, 0xBC);              
	SiiRegWrite(REG_MHLTX_CTL2, 0x3C);              
	SiiRegWrite(REG_MHLTX_CTL4, 0xC8);              
	SiiRegWrite(REG_MHLTX_CTL7, 0x03);              
	SiiRegWrite(REG_MHLTX_CTL8, 0x0A);              
    SiiRegWrite(REG_TMDS_CCTRL, 0x08);              
	SiiRegWrite(REG_USB_CHARGE_PUMP_MHL, 0x03);     
	SiiRegWrite(REG_USB_CHARGE_PUMP, 0x8C);         
	SiiRegWrite(REG_SYS_CTRL1, 0x35);               
	SiiRegWrite(REG_DISC_CTRL5, 0x57);				
	SiiRegWrite(REG_DISC_CTRL9, 0x24);				
	SiiRegWrite(REG_DISC_CTRL1, 0x27);				
	SiiRegWrite(REG_DISC_CTRL3, 0x86);				
	CbusReset();
	InitCBusRegs();
    SiiRegModify(REG_LM_DDC, VID_MUTE, SET_BITS);       
    SiiRegModify(REG_AUDP_TXCTRL, BIT2, SET_BITS);      
}
Exemplo n.º 3
0
void sii9234_register_init(void)
{
    // Power Up
    I2C_WriteByte(0x7A, 0x3D, 0x3F);			// Power up CVCC 1.2V core
    I2C_WriteByte(0x92, 0x11, 0x01);			// Enable TxPLL Clock
    I2C_WriteByte(0x92, 0x12, 0x15);			// Enable Tx Clock Path & Equalizer
    I2C_WriteByte(0x72, 0x08, 0x35);			// Power Up TMDS Tx Core

    I2C_WriteByte(0x92, 0x00, 0x00);			// SIMG: correcting HW default
    I2C_WriteByte(0x92, 0x13, 0x60);			// SIMG: Set termination value
    I2C_WriteByte(0x92, 0x14, 0xF0);			// SIMG: Change CKDT level
    I2C_WriteByte(0x92, 0x4B, 0x06);			// SIMG: Correcting HW default

    // Analog PLL Control
    I2C_WriteByte(0x92, 0x17, 0x07);			// SIMG: PLL Calrefsel
    I2C_WriteByte(0x92, 0x1A, 0x20);			// VCO Cal
    I2C_WriteByte(0x92, 0x22, 0xE0);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x23, 0xC0);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x24, 0xA0);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x25, 0x80);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x26, 0x60);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x27, 0x40);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x28, 0x20);			// SIMG: Auto EQ
    I2C_WriteByte(0x92, 0x29, 0x00);			// SIMG: Auto EQ

    I2C_WriteByte(0x92, 0x4D, 0x02);			// SIMG: PLL Mode Value (order is important)
    I2C_WriteByte(0x92, 0x4C, 0xA0);			// Manual zone control

    I2C_WriteByte(0x72, 0x80, 0x14);			// Enable Rx PLL Clock Value

    I2C_WriteByte(0x92, 0x31, 0x0B);			// SIMG: Rx PLL BW value from I2C BW ~ 4MHz
    I2C_WriteByte(0x92, 0x45, 0x06);			// SIMG: DPLL Mode
    I2C_WriteByte(0x72, 0xA0, 0xD0);			// SIMG: Term mode
    I2C_WriteByte(0x72, 0xA1, 0xFC);			// Disable internal Mobile HD driver

    I2C_WriteByte(0x72, 0xA3, 0xF9);			// SIMG: Output Swing  default EB
    I2C_WriteByte(0x72, 0xA6, 0x0C);			// SIMG: Swing Offset

    I2C_WriteByte(0x72, 0x2B, 0x01);			// Enable HDCP Compliance workaround

    // CBUS & Discovery
    ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3);	// CBUS discovery cycle time for each drive and float = 150us

    I2C_WriteByte(0x72, 0x91, 0xE5);		// Skip RGND detection

    I2C_WriteByte(0x72, 0x94, 0x66);			// 1.8V CBUS VTH & GND threshold

    //set bit 2 and 3, which is Initiator Timeout
    I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);

    // original 3x config
    I2C_WriteByte(0x72, 0xA5, 0x80);			// SIMG: RGND Hysterisis, 3x mode for Beast
    I2C_WriteByte(0x72, 0x95, 0x31);			// RGND & single discovery attempt (RGND blocking)
    I2C_WriteByte(0x72, 0x96, 0x22);			// use 1K and 2K setting

    ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6);		// Force USB ID switch to open

    WriteByteTPI(0x92, 0x46);				// Force MHD mode
    WriteByteTPI(0x93, 0xDC);				// Disable CBUS pull-up during RGND measurement

    ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0);        //daniel test...MHL_INT

    delay_ms(25);
    ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00);		// Release USB ID switch

    I2C_WriteByte(0x72, 0x90, 0x27);			// Enable CBUS discovery

    InitCBusRegs();

    I2C_WriteByte(0x72, 0x05, ASR_VALUE); 		// Enable Auto soft reset on SCDT = 0

    I2C_WriteByte(0x72, 0x0D, 0x1C); 			// HDMI Transcode mode enable
}
static void sii9234_register_init(void)
{
    /*Power Up*/
    I2C_WriteByte(0x7A, 0x3D, 0x3F);	/* Power up CVCC 1.2V core */
    I2C_WriteByte(0x92, 0x11, 0x01);	/* Enable TxPLL Clock*/
    I2C_WriteByte(0x92, 0x12, 0x15);	/* Enable Tx Clock Path & Equalizer*/
    I2C_WriteByte(0x72, 0x08, 0x35);	/* Power Up TMDS Tx Core*/

    I2C_WriteByte(0x92, 0x00, 0x00);	/* SIMG: correcting HW default*/
    I2C_WriteByte(0x92, 0x13, 0x60);	/* SIMG: Set termination value*/
    I2C_WriteByte(0x92, 0x14, 0xF0);	/* SIMG: Change CKDT level*/
    I2C_WriteByte(0x92, 0x4B, 0x06);	/* SIMG: Correcting HW default*/

    /*Analog PLL Control*/
    I2C_WriteByte(0x92, 0x17, 0x07);	/* SIMG: PLL Calrefsel*/
    I2C_WriteByte(0x92, 0x1A, 0x20);	/* VCO Cal*/
    I2C_WriteByte(0x92, 0x22, 0xE0);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x23, 0xC0);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x24, 0xA0);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x25, 0x80);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x26, 0x60);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x27, 0x40);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x28, 0x20);	/* SIMG: Auto EQ*/
    I2C_WriteByte(0x92, 0x29, 0x00);	/* SIMG: Auto EQ*/

    /*I2C_WriteByte(0x92, 0x10, 0xF1);*/
    I2C_WriteByte(0x92, 0x4D, 0x02);	/* SIMG: PLL Mode Value (order is important)*/
    /*I2C_WriteByte(0x92, 0x4D, 0x00);*/
    I2C_WriteByte(0x92, 0x4C, 0xA0);	/* Manual zone control*/

    /*I2C_WriteByte(0x72, 0x80, 0x14);*/	/* Enable Rx PLL Clock Value*/
    I2C_WriteByte(0x72, 0x80, 0x34);

    I2C_WriteByte(0x92, 0x31, 0x0B);	/* SIMG: Rx PLL BW value from I2C BW ~ 4MHz*/
    I2C_WriteByte(0x92, 0x45, 0x06);	/* SIMG: DPLL Mode*/
    I2C_WriteByte(0x72, 0xA0, 0xD0);	/* SIMG: Term mode*/
    I2C_WriteByte(0x72, 0xA1, 0xFC);	/* Disable internal Mobile HD driver*/


    I2C_WriteByte(0x72, 0xA3, 0xEB);	/* SIMG: Output Swing  default EB*/
    I2C_WriteByte(0x72, 0xA6, 0x00);	/* SIMG: Swing Offset*/

    I2C_WriteByte(0x72, 0x2B, 0x01);	/* Enable HDCP Compliance workaround*/

    /*CBUS & Discovery*/
    ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3);/* CBUS discovery cycle time for each drive and float = 150us*/

    I2C_WriteByte(0x72, 0x91, 0xE5);	/* Skip RGND detection*/

    I2C_WriteByte(0x72, 0x94, 0x66);	/* 1.8V CBUS VTH & GND threshold*/

    /*set bit 2 and 3, which is Initiator Timeout*/
    I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);

    /*original 3x config*/
    I2C_WriteByte(0x72, 0xA5, 0x80);	/* SIMG: RGND Hysterisis, 3x mode for Beast*/
    I2C_WriteByte(0x72, 0x95, 0x31);	/* RGND & single discovery attempt (RGND blocking)*/
    I2C_WriteByte(0x72, 0x96, 0x22);	/* use 1K and 2K setting*/

    ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6);		/* Force USB ID switch to open*/

    WriteByteTPI(0x92, 0x46);		/* Force MHD mode*/
    WriteByteTPI(0x93, 0xDC);		/* Disable CBUS pull-up during RGND measurement*/

    ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0);        /*daniel test...MHL_INT*/

    mdelay(25);
    ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00);	/* Release USB ID switch*/

    I2C_WriteByte(0x72, 0x90, 0x27);	/* Enable CBUS discovery*/

    InitCBusRegs();

    I2C_WriteByte(0x72, 0x05, ASR_VALUE);	/* Enable Auto soft reset on SCDT = 0*/

    I2C_WriteByte(0x72, 0x0D, 0x1C);	/* HDMI Transcode mode enable*/
}
///////////////////////////////////////////////////////////////////////////
// WriteInitialRegisterValues
//
//
///////////////////////////////////////////////////////////////////////////
static void WriteInitialRegisterValues (void)
{
	//TX_DEBUG_PRINT(("Drv: WriteInitialRegisterValues\n"));

	// Power Up
	SiiRegWrite(REG_DPD, 0x3F);			// Power up CVCC 1.2V core
	SiiRegWrite(REG_TMDS_CLK_EN, 0x01);			// Enable TxPLL Clock
	SiiRegWrite(REG_TMDS_CH_EN, 0x11);			// Enable Tx Clock Path & Equalizer

	SiiRegWrite(REG_MHLTX_CTL1, 0x10); // TX Source termination ON
	SiiRegWrite(REG_MHLTX_CTL6, 0xBC); // Enable 1X MHL clock output
	SiiRegWrite(REG_MHLTX_CTL2, 0x3C); // TX Differential Driver Config
	SiiRegWrite(REG_MHLTX_CTL4, 0xC8);
	SiiRegWrite(REG_MHLTX_CTL7, 0x03); // 2011-10-10
	SiiRegWrite(REG_MHLTX_CTL8, 0x0A); // PLL bias current, PLL BW Control

	// Analog PLL Control
	SiiRegWrite(REG_TMDS_CCTRL, 0x08);			// Enable Rx PLL clock 2011-10-10 - select BGR circuit for voltage references
	SiiRegWrite(REG_USB_CHARGE_PUMP, 0x8C);		// 2011-10-10 USB charge pump clock
    SiiRegWrite(REG_TMDS_CTRL4, 0x02);

	SiiRegWrite(REG_TMDS0_CCTRL2, 0x00);
	SiiRegModify(REG_DVI_CTRL3, BIT5, 0);      // 2011-10-10
	SiiRegWrite(REG_TMDS_TERMCTRL1, 0x60);

	SiiRegWrite(REG_PLL_CALREFSEL, 0x03);			// PLL Calrefsel
	SiiRegWrite(REG_PLL_VCOCAL, 0x20);			// VCO Cal
	SiiRegWrite(REG_EQ_DATA0, 0xE0);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA1, 0xC0);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA2, 0xA0);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA3, 0x80);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA4, 0x60);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA5, 0x40);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA6, 0x20);			// Auto EQ
	SiiRegWrite(REG_EQ_DATA7, 0x00);			// Auto EQ

	SiiRegWrite(REG_BW_I2C, 0x0A);			// Rx PLL BW ~ 4MHz
	SiiRegWrite(REG_EQ_PLL_CTRL1, 0x06);			// Rx PLL BW value from I2C

	SiiRegWrite(REG_MON_USE_COMP_EN, 0x06);

    // synchronous s/w reset
	SiiRegWrite(REG_ZONE_CTRL_SW_RST, 0x60);			// Manual zone control
	SiiRegWrite(REG_ZONE_CTRL_SW_RST, 0xE0);			// Manual zone control

	SiiRegWrite(REG_MODE_CONTROL, 0x00);			// PLL Mode Value

	SiiRegWrite(REG_SYS_CTRL1, 0x35);			// bring out from power down (script moved this here from above)

	SiiRegWrite(REG_DISC_CTRL2, 0xAD);
	SiiRegWrite(REG_DISC_CTRL5, 0x57);				// 1.8V CBUS VTH 5K pullup for MHL state
	SiiRegWrite(REG_DISC_CTRL6, 0x11);				// RGND & single discovery attempt (RGND blocking)
	SiiRegWrite(REG_DISC_CTRL8, 0x82);				// Ignore VBUS
	SiiRegWrite(REG_DISC_CTRL9, 0x24);				// No OTG, Discovery pulse proceed, Wake pulse not bypassed
	SiiRegWrite(REG_DISC_CTRL4, 0x8C);				// Pull-up resistance off for IDLE state.
	SiiRegWrite(REG_DISC_CTRL1, 0x27);				// Enable CBUS discovery
	SiiRegWrite(REG_DISC_CTRL7, 0x20);				// use 1K only setting
	SiiRegWrite(REG_DISC_CTRL3, 0x86);				// MHL CBUS discovery

	CLR_BIT(REG_INT_CTRL, 6);//change hpd out pin from defult open-drain to push-pull by garyyuan
	if (fwPowerState != TX_POWER_STATE_D3) {			// Don't force HPD to 0 during wake-up from D3
		SiiRegModify(REG_INT_CTRL, BIT5 | BIT4, BIT4);	// Force HPD to 0 when not in MHL mode.
		}

	SiiRegWrite(REG_SRST, 0x84); 					// Enable Auto soft reset on SCDT = 0

	SiiRegWrite(REG_DCTL, 0x1C); 		// HDMI Transcode mode enable

	CbusReset();

	InitCBusRegs();
}