/**
* This function is used to lock access to critical sections when lwipopt.h
* defines SYS_LIGHTWEIGHT_PROT. It disables interrupts and returns a value
* indicating the interrupt enable state when the function entered. This
* value must be passed back on the matching call to sys_arch_unprotect().
*
* @return the interrupt level when the function was entered.
*/
sys_prot_t
sys_arch_protect(void)
{
volatile sys_prot_t status;
status = (IntMasterStatusGet() & 0xFF);
IntMasterIRQDisable();
return status;
}
unsigned char IntDisable(void)
{
unsigned char status;
/* Reads the current status.*/
status = (IntMasterStatusGet() & 0xFF);
/* Disable the Interrupts.*/
IntMasterIRQDisable();
return status;
}
/*
** Enter the desired power save mode
*/
void PowerSaveModeEnter(deepSleepData dsData, unsigned int slpMode)
{
unsigned int i = 0;
unsigned int index = 0;
unsigned int noOfElements = sizeof(pmModuleList)/sizeof(pmModuleList[0]);
PeripheralsContextSave(slpMode, wakeSource);
PeripheralsHalt();
dsData.dsDataBits.wakeSources = wakeSource;
/* Configure CMD_ID and other parameters which are to be
** communicated with CM3 */
configIPCRegs(dsData);
syncCm3();
if(SLEEP_STAND_BY_MODE == slpMode)
{
/* Enable wake source interupt */
enableStandbyWakeSrc(dsData.dsDataBits.wakeSources);
}
else
{
/* Enable wake source */
enableWakeSource(dsData.dsDataBits.wakeSources);
}
/* Include MPU Clock in the disable list */
for(index = 0; index < noOfElements; index++)
{
if(CLK_MPU_CLK == pmModuleList[index].module)
{
pmModuleList[index].select = TRUE;
}
}
/* Disable clock */
while(true != disableSelModuleClock(pmModuleList,
(sizeof(pmModuleList)/sizeof(pmModuleList[0]))));
/* Configure for minimum OPP supported by SoC */
ConfigMinimumOPP();
disableModuleClock(CLK_I2C0, TRUE);
/* Disable IRQ */
IntMasterIRQDisable();
if(SLEEP_MODE_DS0 == slpMode)
{
PowerDownConfig();
}
/*
** Save A8 context
** WFI
** Restore A8 context
*/
saveRestoreContext(slpMode, deviceVersion);
/* Enable Timer3 for DS2 */
enableModuleClock(CLK_TIMER3);
/* Enable IRQ */
IntMasterIRQEnable();
enableModuleClock(CLK_I2C0);
/* Restore OPP configuration */
DemoOppChange(mpuOpp);
/* Exclude MPU Clock from the disable list */
for(index = 0; index < noOfElements; index++)
{
if(CLK_MPU_CLK == pmModuleList[index].module)
{
pmModuleList[index].select = FALSE;
}
}
/* Device clock enable */
enableSelModuleClock(pmModuleList,
(sizeof(pmModuleList)/sizeof(pmModuleList[0])));
EDMAModuleClkConfig();
/* disable wake source */
if(SLEEP_STAND_BY_MODE == slpMode)
{
disableStandbyWakeSrc(dsData.dsDataBits.wakeSources);
}
else
{
disableWakeSource(dsData.dsDataBits.wakeSources);
}
PeripheralsContextRestore(slpMode, dsData.dsDataBits.wakeSources);
PeripheralsResume();
/*
** Print string name of the sleep mode.
*/
ConsoleUtilsPrintf("\n\r%s", sleepModeStrMap[slpMode].str);
/* Check the DS status */
if(PM_CMD_FAIL == (readCmdStatus() & (PM_CMD_FAIL)))
{
ConsoleUtilsPrintf(" attempt failed");
}
else
{
ConsoleUtilsPrintf(" attempt passed");
}
/* Reset CM3 State Machine */
configIPCRegs(dsDataM3reset);
syncCm3();
if(slpMode & SLEEP_MODE_DS1)
{
/* delay to reduce the frequency of sleep/wake cycle for DS1 */
delay(500);
}
for(i = 0; i < 2; i++)
{
x_data[i] = 0;
y_data[i] = 0;
}
/* Reset sleep trigger flag */
IsTSPress = 0;
}
void configEMIFOPP100(void)
{
/* Disable interrupts */
IntMasterIRQDisable();
IntMasterFIQDisable();
/* DDR2 in SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) |=
((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Give a delay */
//for(loopIdx = 0;(loopIdx < PM_DELAY_COUNT);loopIdx++) {}
/* PLL Configuration */
/* MN bypass */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_MN_BYP_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS);
/* M & N */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKSEL_DPLL_DDR) =
(PM_OPP100_DDR_M << CM_WKUP_CM_CLKSEL_DPLL_DDR_DPLL_MULT_SHIFT) |
(PM_OPP100_DDR_N);
/* M2 */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) &
(~CM_WKUP_CM_DIV_M2_DPLL_DDR_DPLL_CLKOUT_DIV)) | (PM_OPP100_DDR_M2);
/* PLL Relock */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_LOCK_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK_DPLL_LOCKED);
/* EMIF PRCM */
/* Enable EMIF4DC Firewall clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) &
CM_PER_EMIF_FW_CLKCTRL_MODULEMODE) | CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE;
/* Enable EMIF4DC clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) & (~CM_PER_EMIF_CLKCTRL_MODULEMODE)) |
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE;
/* Poll for module is functional */
while(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) !=
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE);
/*CMD REG PHY*/
HWREG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD2_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
/*DATA0 and DATA1 PHY config*/
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
/* IO configuration*/
//IO to work for mDDR
//HWREG(SOC_CONTROL_REGS + CONTROL_DDR_IO_CTRL) |= 0x10000000;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(2)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
//CKE controlled by EMIF/DDR_PHY
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CKE_CTRL) |= 0x00000001;
/*EMIF Timings*/
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1_SHDW) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_2) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1_SHDW) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2_SHDW) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3_SHDW) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG) = OPP100_DDR2_SDRAM_CONFIG;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG_2) = OPP100_DDR2_SDRAM_CONFIG;
/* DDR out of SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) &=
~((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Enable interrupts */
IntMasterFIQEnable();
IntMasterIRQEnable();
}
/*
** Main function. The application starts here.
*/
int main(void)
{
unsigned char rxByte;
unsigned int value = (unsigned int)E_FAIL;
#ifdef __TMS470__
/* Relocate the required section to internal RAM */
memcpy((void *)(&relocstart), (const void *)(&iram_start),
(unsigned int)(&iram_size));
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma section = "CodeRelocOverlay"
#pragma section = "DataRelocOverlay"
#pragma section = "DataOverlayBlk"
#pragma section = "CodeOverlayBlk"
char* srcAddr = (__section_begin("CodeRelocOverlay"));
char* endAddr = (__section_end("DataRelocOverlay"));
memcpy((void *)(__section_begin("CodeRelocOverlay")),
(const void *)(__section_begin("CodeOverlayBlk")),
endAddr - srcAddr);
#else
memcpy((void *)&(relocstart), (const void *)&(iram_start),
(unsigned int)(((&(relocend)) -
(&(relocstart))) * (sizeof(unsigned int))));
#endif
MMUConfigAndEnable();
/* Enable Instruction Cache */
CacheEnable(CACHE_ALL);
PeripheralsSetUp();
/* Initialize the ARM Interrupt Controller */
IntAINTCInit();
/* Register the ISRs */
Timer2IntRegister();
Timer4IntRegister();
EnetIntRegister();
RtcIntRegister();
CM3IntRegister();
HSMMCSDIntRegister();
IntRegister(127, dummyIsr);
IntMasterIRQEnable();
pageIndex = 0;
prevAction = 0;
/* Enable system interrupts */
IntSystemEnable(SYS_INT_RTCINT);
IntPrioritySet(SYS_INT_RTCINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntPrioritySet(SYS_INT_3PGSWTXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT2);
IntPrioritySet(SYS_INT_TINT2, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT4);
IntPrioritySet(SYS_INT_TINT4, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_MMCSD0INT);
IntPrioritySet(SYS_INT_MMCSD0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_EDMACOMPINT);
IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntPrioritySet(SYS_INT_M3_TXEV, 0, AINTC_HOSTINT_ROUTE_IRQ );
IntSystemEnable(SYS_INT_M3_TXEV);
IntSystemEnable(127);
IntPrioritySet(127, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_UART0INT);
IntPrioritySet(SYS_INT_UART0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_UART0INT, uartIsr);
/* GPIO interrupts */
IntSystemEnable(SYS_INT_GPIOINT0A);
IntPrioritySet(SYS_INT_GPIOINT0A, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_GPIOINT0A, gpioIsr);
IntSystemEnable(SYS_INT_GPIOINT0B);
IntPrioritySet(SYS_INT_GPIOINT0B, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_GPIOINT0B, gpioIsr);
BoardInfoInit();
deviceVersion = DeviceVersionGet();
CM3EventsClear();
CM3LoadAndRun();
waitForM3Txevent();
/* Initialize console for communication with the Host Machine */
ConsoleUtilsInit();
/*
** Select the console type based on compile time check
** Note: This example is not fully complaint to semihosting. It is
** recommended to use Uart console interface only.
*/
ConsoleUtilsSetType(CONSOLE_UART);
/* Print Board and SoC information on console */
ConsoleUtilsPrintf("\n\r Board Name : %s", BoardNameGet());
ConsoleUtilsPrintf("\n\r Board Version : %s", BoardVersionGet());
ConsoleUtilsPrintf("\n\r SoC Version : %d", deviceVersion);
/* On CM3 init firmware version is loaded onto the IPC Message Reg */
ConsoleUtilsPrintf("\n CM3 Firmware Version: %d", readCM3FWVersion());
I2CIntRegister(I2C_0);
IntPrioritySet(SYS_INT_I2C0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_I2C0INT);
I2CInit(I2C_0);
IntSystemEnable(SYS_INT_TINT1_1MS);
IntPrioritySet(SYS_INT_TINT1_1MS, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_TINT1_1MS,clearTimerInt);
configVddOpVoltage();
RtcInit();
HSMMCSDContolInit();
DelayTimerSetup();
initializeTimer1();
ConsoleUtilsPrintf("\r\n After intializing timer");
Timer2Config();
Timer4Config();
LedIfConfig();
MailBoxInit();
Timer2IntEnable();
Timer4IntEnable();
RtcSecIntEnable();
Timer4Start();
while(FALSE == tmr4Flag);
tmr4Flag = FALSE;
Timer4Stop();
ConsoleUtilsPrintf("\n\r Configuring for maximum OPP");
mpuOpp = ConfigMaximumOPP();
mpuFreq = FrequencyGet(mpuOpp);
mpuVdd1 = VddVoltageGet(mpuOpp);
PrintConfigDVFS();
/* Create menu page */
pageIndex = MENU_IDX_MAIN;
ActionEnetInit();
/*
** Loop for ever. Necessary actions shall be taken
** after detecting the click.
*/
while(1)
{
/*
** Check for any any activity on Uart Console and process it.
*/
if (true == UARTCharsAvail(SOC_UART_0_REGS))
{
/* Receiving bytes from the host machine through serial console. */
rxByte = UARTGetc();
/*
** Checking if the entered character is a carriage return.
** Pressing the 'Enter' key on the keyboard executes a
** carriage return on the serial console.
*/
if('\r' == rxByte)
{
ConsoleUtilsPrintf("\n");
UartAction(value);
value = (unsigned int)E_FAIL;
rxByte = 0;
}
/*
** Checking if the character entered is one among the decimal
** number set 0,1,2,3,....9
*/
if(('0' <= rxByte) && (rxByte <= '9'))
{
ConsoleUtilsPrintf("%c", rxByte);
if((unsigned int)E_FAIL == value)
{
value = 0;
}
value = value*10 + (rxByte - 0x30);
}
}
/*
** Check if click is detected
*/
if(clickIdx != 0)
{
/*
** Take the Action for click
*/
ClickAction();
clickIdx = 0;
}
/*
** Check if the Timer Expired
*/
if(TRUE == tmrFlag)
{
/* Toggle the LED state */
LedToggle();
tmrFlag = FALSE;
}
/*
** Check if RTC Time is set
*/
if(TRUE == rtcSetFlag)
{
if(TRUE == rtcSecUpdate)
{
rtcSecUpdate = FALSE;
RtcTimeCalDisplay();
ConsoleUtilsPrintf(" --- Selected: ");
}
}
if(TRUE == tmr4Flag)
{
tmr4Flag = FALSE;
/* Make sure that interrupts are disabled and no lwIP functions
are executed while calling an lwIP exported API */
IntMasterIRQDisable();
etharp_tmr();
IntMasterIRQEnable();
}
}
}
