static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b1 { UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { STORE_RM32(modrm, src); cpustate->ZF = 1; CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T); } else { REG32(EAX) = dst; cpustate->ZF = 0; CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F); } } else { UINT32 ea = GetEA(cpustate,modrm); UINT32 dst = READ32(cpustate,ea); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { WRITE32(cpustate,ea, src); cpustate->ZF = 1; CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG32(EAX) = dst; cpustate->ZF = 0; CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } }
void i386_device::i486_cmpxchg_rm32_r32() // Opcode 0x0f b1 { UINT8 modrm = FETCH(); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { STORE_RM32(modrm, src); m_ZF = 1; CYCLES(CYCLES_CMPXCHG_REG_REG_T); } else { REG32(EAX) = dst; m_ZF = 0; CYCLES(CYCLES_CMPXCHG_REG_REG_F); } } else { UINT32 ea = GetEA(modrm,0); UINT32 dst = READ32(ea); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { WRITE32(ea, src); m_ZF = 1; CYCLES(CYCLES_CMPXCHG_REG_MEM_T); } else { REG32(EAX) = dst; m_ZF = 0; CYCLES(CYCLES_CMPXCHG_REG_MEM_F); } } }
static void I486OP(xadd_rm32_r32)(i386_state *cpustate) // Opcode 0x0f c1 { UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); STORE_RM32(modrm, dst + src); STORE_REG32(modrm, dst); CYCLES(cpustate,CYCLES_XADD_REG_REG); } else { UINT32 ea = GetEA(cpustate,modrm); UINT32 dst = READ32(cpustate,ea); UINT32 src = LOAD_REG32(modrm); WRITE32(cpustate,ea, dst + src); STORE_REG32(modrm, dst); CYCLES(cpustate,CYCLES_XADD_REG_MEM); } }
void i386_device::i486_xadd_rm32_r32() // Opcode 0x0f c1 { UINT8 modrm = FETCH(); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); STORE_REG32(modrm, dst); STORE_RM32(modrm, dst + src); CYCLES(CYCLES_XADD_REG_REG); } else { UINT32 ea = GetEA(modrm,1); UINT32 dst = READ32(ea); UINT32 src = LOAD_REG32(modrm); WRITE32(ea, dst + src); STORE_REG32(modrm, dst); CYCLES(CYCLES_XADD_REG_MEM); } }
static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 { UINT8 modrm = FETCH(cpustate); UINT32 address, ea; switch( (modrm >> 3) & 0x7 ) { case 0: /* SGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address ); } else { ea = GetEA(cpustate,modrm); } WRITE16(cpustate,ea, cpustate->gdtr.limit); WRITE32(cpustate,ea + 2, cpustate->gdtr.base); CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ { if (modrm >= 0xc0) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address ); } else { ea = GetEA(cpustate,modrm); } WRITE16(cpustate,ea, cpustate->idtr.limit); WRITE32(cpustate,ea + 2, cpustate->idtr.base); CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address ); } else { ea = GetEA(cpustate,modrm); } cpustate->gdtr.limit = READ16(cpustate,ea); cpustate->gdtr.base = READ32(cpustate,ea + 2); CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address ); } else { ea = GetEA(cpustate,modrm); } cpustate->idtr.limit = READ16(cpustate,ea); cpustate->idtr.base = READ32(cpustate,ea + 2); CYCLES(cpustate,CYCLES_LIDT); break; } case 7: /* INVLPG */ { // Nothing to do ? break; } default: fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } }
static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 { UINT8 modrm = FETCH(cpustate); UINT32 address, ea; switch( (modrm >> 3) & 0x7 ) { case 0: /* SGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address, 1 ); } else { ea = GetEA(cpustate,modrm,1); } WRITE16(cpustate,ea, cpustate->gdtr.limit); WRITE32(cpustate,ea + 2, cpustate->gdtr.base); CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ { if (modrm >= 0xc0) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address, 1 ); } else { ea = GetEA(cpustate,modrm,1); } WRITE16(cpustate,ea, cpustate->idtr.limit); WRITE32(cpustate,ea + 2, cpustate->idtr.base); CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if(PROTECTED_MODE && cpustate->CPL) FAULT(FAULT_GP,0) if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address, 0 ); } else { ea = GetEA(cpustate,modrm,0); } cpustate->gdtr.limit = READ16(cpustate,ea); cpustate->gdtr.base = READ32(cpustate,ea + 2); CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if(PROTECTED_MODE && cpustate->CPL) FAULT(FAULT_GP,0) if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); ea = i386_translate( cpustate, CS, address, 0 ); } else { ea = GetEA(cpustate,modrm,0); } cpustate->idtr.limit = READ16(cpustate,ea); cpustate->idtr.base = READ32(cpustate,ea + 2); CYCLES(cpustate,CYCLES_LIDT); break; } case 4: /* SMSW */ { if( modrm >= 0xc0 ) { STORE_RM32(modrm, cpustate->cr[0] & 0xffff); CYCLES(cpustate,CYCLES_SMSW_REG); } else { /* always 16-bit memory operand */ ea = GetEA(cpustate,modrm,1); WRITE16(cpustate,ea, cpustate->cr[0]); CYCLES(cpustate,CYCLES_SMSW_MEM); } break; } case 7: /* INVLPG */ { // Nothing to do ? break; } default: fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } }