/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
VOID *TrinityPciePortPtr;
VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
if ( Status!= AGESA_SUCCESS) {
// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
ASSERT(FALSE);
return;
}
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
sizeof(Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
}
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
{
AGESA_STATUS Status;
VOID *LlanoPcieComplexListPtr;
VOID *LlanoPciePortPtr;
VOID *LlanoPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Llano);
LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (LlanoPcieComplexListPtr,
0,
sizeof(Llano),
&InitEarly->StdHeader);
LibAmdMemFill (LlanoPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (LlanoPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader);
LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
return AGESA_SUCCESS;
}
AGESA_STATUS
GfxInitAtPost (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_POST_PARAMS *PostParamsPtr;
GFX_CARD_CARD_INFO GfxDiscreteCardInfo;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
if (GfxLibIsControllerPresent (StdHeader)) {
if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
if (GfxDiscreteCardInfo.PciGfxCardBitmap != 0 ||
(GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & GfxDiscreteCardInfo.PcieGfxCardBitmap) !=
GfxDiscreteCardInfo.AmdPcieGfxCardBitmap) {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n");
}
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
Gfx->GfxFusedOff = TRUE;
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status);
return Status;
}
/**
* For event HT_EVENT_COH_MPCAP_MISMATCH
*
* @param[in] Node The node from which a new node was discovered
* @param[in] Link The link from that node
* @param[in] Cap The aggregate system MP Capability
* @param[in] Nodes The total number of nodes found so far
* @param[in] State our State
*
*/
VOID
NotifyFatalCohMpCapMismatch (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Cap,
IN UINT8 Nodes,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.Node = Node;
Evt.Link = Link;
Evt.SysMpCap = Cap;
Evt.TotalNodes = Nodes;
setEventNotify (AGESA_CRITICAL,
HT_EVENT_COH_MPCAP_MISMATCH,
(UINT8 *)&Evt, State);
}
/**
* For event HT_EVENT_COH_NODE_DISCOVERED
*
* @param[in] Node Node from which a new node was discovered
* @param[in] Link The link to that new node
* @param[in] NewNode The new node's id
* @param[in] TempRoute Temporarily, during discovery, the new node is accessed at this id.
* @param[in] State our State
*
*/
VOID
NotifyInfoCohNodeDiscovered (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 NewNode,
IN UINT8 TempRoute,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_COH_NODE_DISCOVERED Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.Node = Node;
Evt.Link = Link;
Evt.NewNode = NewNode;
Evt.TempRoute = TempRoute;
setEventNotify (AGESA_SUCCESS,
HT_EVENT_COH_NODE_DISCOVERED,
(UINT8 *)&Evt, State);
}
/**
* For event HT_EVENT_OPT_LINK_PAIR_EXCEED
*
* @param[in] NodeA One of the nodes connected
* @param[in] NodeB The other connected node
* @param[in] MasterLink its unusable Masterlink
* @param[in] AltLink its unusable Alternate link
* @param[in] State our State
*
*/
VOID
NotifyWarningOptLinkPairExceed (
IN UINT32 NodeA,
IN UINT32 NodeB,
IN UINT32 MasterLink,
IN UINT32 AltLink,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.NodeA = NodeA;
Evt.MasterLink = MasterLink;
Evt.NodeB = NodeB;
Evt.AltLink = AltLink;
setEventNotify (AGESA_WARNING,
HT_EVENT_OPT_LINK_PAIR_EXCEED,
(UINT8 *)&Evt, State);
}
/**
* For event HT_EVENT_OPT_UNUSED_LINKS
*
* @param[in] NodeA One of the nodes connected
* @param[in] NodeB The other connected node
* @param[in] LinkA its unusable link
* @param[in] LinkB its unusable link
* @param[in] State our State
*
*/
VOID
NotifyWarningOptUnusedLinks (
IN UINT32 NodeA,
IN UINT32 LinkA,
IN UINT32 NodeB,
IN UINT32 LinkB,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_OPT_UNUSED_LINKS Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.NodeA = NodeA;
Evt.LinkA = LinkA;
Evt.NodeB = NodeB;
Evt.LinkB = LinkB;
setEventNotify (AGESA_WARNING,
HT_EVENT_OPT_UNUSED_LINKS,
(UINT8 *)&Evt, State);
}
/**
* For event HT_EVENT_NCOH_DEVICE_FAILED
*
* @param[in] Node The node on which the chain is located
* @param[in] Link The link from that node
* @param[in] Depth Position on chain
* @param[in] Id The Id which was attempted to assigned
* @param[in] State our State
*
*/
VOID
NotifyErrorNcohDeviceFailed (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Depth,
IN UINT8 Id,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.Node = Node;
Evt.Link = Link;
Evt.Depth = Depth;
Evt.AttemptedBuid = Id;
setEventNotify (AGESA_ERROR,
HT_EVENT_NCOH_DEVICE_FAILED,
(UINT8 *)&Evt, State);
}
/**
* For event HT_EVENT_NCOH_BUID_EXCEED
*
* @param[in] Node The node on which the chain is located
* @param[in] Link The link from that node
* @param[in] Depth Position on chain
* @param[in] Id The Id which was attempted to assigned
* @param[in] Units The number of units in this device
* @param[in] State our State
*
*/
VOID
NotifyErrorNcohBuidExceed (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Depth,
IN UINT8 Id,
IN UINT8 Units,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_NCOH_BUID_EXCEED Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
Evt.Node = Node;
Evt.Link = Link;
Evt.Depth = Depth;
Evt.CurrentBuid = Id;
Evt.UnitCount = Units;
setEventNotify (AGESA_ERROR,
HT_EVENT_NCOH_BUID_EXCEED,
(UINT8 *)&Evt, State);
}
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (PcieComplexListPtr,
0,
sizeof(PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader);
PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
PcieComplexListPtr->SocketId = 0;
PcieComplexListPtr->PciePortList = PortList;
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
return AGESA_SUCCESS;
}
/**
* For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
*
* @param[in] Node The node from which a new node was discovered
* @param[in] Link The link from that node
* @param[in] Nodes The total number of nodes found so far
* @param[in] State our State
*
*/
VOID
NotifyFatalCohProcessorTypeMix (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Nodes,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
IDS_HDT_CONSOLE (HT_TRACE, "Illegal Processor Type Mix.\n");
Evt.Node = Node;
Evt.Link = Link;
Evt.TotalNodes = Nodes;
setEventNotify (AGESA_CRITICAL,
HT_EVENT_COH_PROCESSOR_TYPE_MIX,
(UINT8 *)&Evt, State);
}
/**
*
* FeatureLeveling
*
* CPU feature leveling. Set least common features set of all CPUs
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
*/
VOID
FeatureLeveling (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Socket;
UINT32 Core;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
BOOLEAN *FirstTime;
BOOLEAN *NeedLeveling;
AGESA_STATUS IgnoredSts;
CPU_FEATURES_LIST *globalCpuFeatureList;
AP_TASK TaskPtr;
ASSERT (IsBsp (StdHeader, &IgnoredSts));
GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
*FirstTime = TRUE;
*NeedLeveling = FALSE;
LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
if (Socket != BscSocket) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
if (*NeedLeveling) {
TaskPtr.FuncAddress.PfApTaskI = WriteFeatures;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
}
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
}
}
BOOLEAN
PcieTopologyIsGen3SupportedV5 (
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
UINT8 LaneNibbleArray [4];
UINT32 LaneBitmap;
UINT8 Nibble;
UINT8 NibbleBitmap;
PCIe_ENGINE_CONFIG *Engine;
LibAmdMemFill (&LaneNibbleArray[0], 0x00, sizeof (LaneNibbleArray), PcieConfigGetStdHeader (Wrapper));
Engine = PcieConfigGetChildEngine (Wrapper);
while (Engine != NULL) {
LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Engine);
for (Nibble = 0; Nibble < 4; Nibble++) {
NibbleBitmap = (0xF << (Nibble * 4));
if ((LaneBitmap & NibbleBitmap) != 0) {
if (++LaneNibbleArray [Nibble] > 1) {
return FALSE;
}
}
}
Engine = PcieLibGetNextDescriptor (Engine);
}
return TRUE;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled;
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
if (Status != AGESA_SUCCESS) {
/* agesawrapper_amdreadeventlog(); */
ASSERT(Status == AGESA_SUCCESS);
}
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
LibAmdMemFill (&FchParams,
0,
sizeof (FchParams),
&StdHeader);
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
BOOLEAN
MemS3ResumeConstructNBBlockC32 (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
)
{
INT32 i;
MEM_NB_BLOCK *NBPtr;
NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
//
// Determine if this is the expected NB Type
//
GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
return FALSE;
}
NBPtr->MemPtr = MemPtr;
NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
NBPtr->Dct = 0;
NBPtr->Channel = 0;
NBPtr->Ganged = FALSE;
NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
for (i = 0; i < EnumSize; i++) {
NBPtr->IsSupported[i] = FALSE;
}
for (i = 0; i < NumberOfHooks; i++) {
NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
}
LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
NBPtr->SwitchDCT = MemNSwitchDCTNb;
NBPtr->SwitchChannel = MemNSwitchChannelNb;
NBPtr->GetBitField = MemNGetBitFieldNb;
NBPtr->SetBitField = MemNSetBitFieldNb;
NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32;
((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32);
MemNSwitchDCTNb (NBPtr, 0);
return TRUE;
}
BOOLEAN
MemNInitPmuSramMsgBlockKV (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
LOCATE_HEAP_PTR LocHeap;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PMU_SRAM_MSG_BLOCK_KV *PmuSramMsgBlockPtr;
LocHeap.BufferHandle = AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE;
if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
PmuSramMsgBlockPtr = (PMU_SRAM_MSG_BLOCK_KV *) LocHeap.BufferPtr;
} else {
// Allocate temporary buffer for PMU SRAM Message Block
AllocHeapParams.RequestedBufferSize = sizeof (PMU_SRAM_MSG_BLOCK_KV);
AllocHeapParams.BufferHandle = AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
if (HeapAllocateBuffer (&AllocHeapParams, &(NBPtr->MemPtr->StdHeader)) != AGESA_SUCCESS) {
return FALSE; // Could not allocate heap for PMU SRAM Message BLock.
}
PmuSramMsgBlockPtr = (PMU_SRAM_MSG_BLOCK_KV *) AllocHeapParams.BufferPtr;
}
LibAmdMemFill ((VOID *)PmuSramMsgBlockPtr, 0, (UINTN)sizeof (PMU_SRAM_MSG_BLOCK_KV), &(NBPtr->MemPtr->StdHeader));
return TRUE;
}
AGESA_STATUS
GfxConfigPostInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GFX_PLATFORM_CONFIG *Gfx;
AMD_POST_PARAMS *PostParamsPtr;
AGESA_STATUS Status;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
ASSERT (Gfx != NULL);
if (Gfx != NULL) {
LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
if (GnbBuildOptions.IgfxModeAsPcieEp) {
Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
} else {
Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
}
Gfx->StdHeader = StdHeader;
Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
Gfx->ForceGfxMode = GfxEnableAuto;
Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
Gfx->GmcClockGating = OptionEnabled;
Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGateStutterOnly ? GmcPowerGatingStutterOnly : GmcPowerGatingWidthStutter;
Gfx->UmaSteering = Garlic;
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
/**
* For event HT_EVENT_HW_HTCRC
*
* @param[in] Node The node on which the error is reported
* @param[in] Link The link from that node
* @param[in] LaneMask The lanes which had CRC
* @param[in] State our State
*
*/
VOID
NotifyAlertHwHtCrc (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 LaneMask,
IN STATE_DATA *State
)
{
HT_EVENT_DATA_HW_HT_CRC Evt;
// Zero out the event data
LibAmdMemFill (
&Evt,
0,
(sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
State->ConfigHandle
);
IDS_HDT_CONSOLE (HT_TRACE, "CRC Error on Node %d Link %d lanes %x.\n", Node, Link, LaneMask);
Evt.Node = Node;
Evt.Link = Link;
Evt.LaneMask = LaneMask;
setEventNotify (AGESA_ALERT,
HT_EVENT_HW_HTCRC,
(UINT8 *)&Evt, State);
}
/**
*
* Get Ids Performance analysis table pointer in the AGESA Heap.
*
* @param[in,out] StdHeader The Pointer of AGESA Header
* @param[in] TestPoint Progress indicator value, see @ref AGESA_TP
*
* @retval AGESA_SUCCESS Success to get the pointer of Performance analysis Table.
* @retval AGESA_ERROR Fail to get the pointer of Performance analysis Table.
* @retval AGESA_UNSUPPORTED Get an exclude testpoint
*
**/
AGESA_STATUS
IdsPerfTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN AGESA_TP TestPoint
)
{
AGESA_STATUS status;
UINT8 Index;
UINT8 i;
TP_Perf_STRUCT *PerfTableEntry;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT64 CurrentTsc;
// Exclude some testpoint which may cause deadloop
for (i = 0; i < (sizeof (IdsPerfExcludeTp) / sizeof (AGESA_TP)); i++) {
if (TestPoint == IdsPerfExcludeTp[i]) {
return AGESA_UNSUPPORTED;
}
}
//if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop
if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) {
LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status == AGESA_SUCCESS) {
PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr);
} else {
AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT);
AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr);
LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader);
}
Index = PerfTableEntry ->Index;
//TPPerfUnit doesn't need to check, it may used for multiple time, used to check the time
// consumption of each perf measure routine.
if ((TestPoint != TpPerfUnit)) {
for (i = 0; i < Index; i++) {
if ((UINT8) TestPoint == PerfTableEntry ->TP[i].TestPoint) {
return AGESA_SUCCESS;
}
}
}
PerfTableEntry ->TP[Index].TestPoint = (UINT8) TestPoint;
PerfTableEntry ->TP[Index].StartTsc = CurrentTsc;
PerfTableEntry ->Index = ++Index;
}
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
}
S3DataType = S3DataTypeNonVolatile;
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = NULL;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
OemPostParams(PostParams);
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow
// the compiler to flag the error if CONFIG_GFXUMA is not set.
PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (UINT16)(0xD0000000 >> 24);
status = AmdInitPost (PostParams);
printk(
BIOS_SPEW,
"setup_uma_memory: umamode %s\n",
(PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" :
(PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" :
(PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" :
"unknown"
);
printk(
BIOS_SPEW,
"setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n",
(unsigned long long)(PostParams->MemConfig.SysLimit) << 16,
(unsigned long)(PostParams->MemConfig.BottomIo) << 16
);
printk(
BIOS_SPEW,
"setup_uma_memory: uma size %luMB, uma start 0x%08lx\n",
(unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16),
(unsigned long)(PostParams->MemConfig.UmaBase) << 16
);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
UINT32
PcieLanesToPowerDownPllInL1 (
IN UINT8 PllPowerUpLatency,
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LaneGroupExitLatency [4];
UINT32 LaneBitmapForPllOffInL1;
PCIe_ENGINE_CONFIG *EngineList;
UINTN Index;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n");
LaneBitmapForPllOffInL1 = 0;
if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) {
if (Wrapper->Features.PllOffInL1 != 0) {
LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie));
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
PCIe_ASPM_LATENCY_INFO LinkLatencyInfo;
UINT32 ActiveLanesBitmap;
UINT32 HotplugLanesBitmap;
if (EngineList->EngineData.EngineType == PciePortEngine) {
LinkLatencyInfo.MaxL1ExitLatency = 0;
LinkLatencyInfo.MaxL0sExitLatency = 0;
ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList);
HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList);
if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) {
PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
}
if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) {
LinkLatencyInfo.MaxL1ExitLatency = 0xff;
}
IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap);
for (Index = 0; Index < 4; Index++) {
if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) {
if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
}
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
LaneBitmapForPllOffInL1 = 0;
for (Index = 0; Index < 4; Index++) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
}
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n");
return LaneBitmapForPllOffInL1;
}
/**
*
* Get Ids Performance analysis table pointer in the AGESA Heap.
*
* @param[in] LineInFile ((FILECODE) shift 16)+ Line number
* @param[in] Description ID for Description define idsperf.h
* @param[in,out] StdHeader The Pointer of AGESA Header
*
* @retval AGESA_SUCCESS Success to get the pointer of Performance analysis Table.
* @retval AGESA_ERROR Fail to get the pointer of Performance analysis Table.
* @retval AGESA_UNSUPPORTED Get an exclude testpoint
*
**/
AGESA_STATUS
IdsPerfTimestamp (
IN UINT32 LineInFile,
IN UINT32 Description,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
UINT32 Index;
TP_Perf_STRUCT *PerfTableEntry;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT64 TscAtBegining;
UINT64 TscAtEnd;
//if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop
if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) {
IdsGetGtsc (&TscAtBegining, StdHeader);
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status == AGESA_SUCCESS) {
PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr);
} else {
AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT);
AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr);
LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader);
PerfTableEntry->Signature = 'FREP';
PerfTableEntry->Version = IDS_PERF_VERSION;
}
Index = PerfTableEntry ->Index;
if (Index >= MAX_PERFORMANCE_UNIT_NUM - 1) {
ASSERT (FALSE);
return AGESA_WARNING;
}
// Read GTSC again, so we could calculate the time consumed by this routine
IdsGetGtsc (&TscAtEnd, StdHeader);
PerfTableEntry ->TP[Index].LineInFile = LineInFile;
PerfTableEntry ->TP[Index].Description = Description;
PerfTableEntry ->TP[Index].StartTsc = TscAtBegining - PerfTableEntry ->TP[MAX_PERFORMANCE_UNIT_NUM - 1].StartTsc;
PerfTableEntry ->TP[MAX_PERFORMANCE_UNIT_NUM - 1].StartTsc += TscAtEnd - TscAtBegining; // Using the last TP to record the total time consumed by this routine
PerfTableEntry ->Index = ++Index;
}
return AGESA_SUCCESS;
}
AGESA_STATUS
GnbCableSafeEntry (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
UINT8 HdpIndex;
UINT8 CurrentIndex;
GNB_CABLE_SAFE_DATA CableSafeData;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
Status = AGESA_SUCCESS;
if (GnbCableSafeIsSupported (StdHeader)) {
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
DdiEngineList[HdpIndex] = NULL;
}
LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
GnbCableSafeGetConnectorInfoArrayCallback,
DdiEngineList,
Pcie
);
CurrentIndex = 0;
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
if (DdiEngineList [HdpIndex] != NULL) {
CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
CurrentIndex++;
}
}
CableSafeData.Config.Enable = 0x1;
CableSafeData.Config.DebounceFilter = 0x2;
CableSafeData.Config.SoftPeriod = 0x4;
CableSafeData.Config.Unit = 0x1;
CableSafeData.Config.Period = 0xf424;
NbSmuRcuRegisterWrite (
SMUx0B_x85D0_ADDRESS,
(UINT32*) &CableSafeData,
sizeof (CableSafeData) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuServiceRequest (0x05, TRUE, StdHeader);
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
return Status;
}
VOID
MemRecUFillTrainPattern (
IN TRAIN_PATTERN Pattern,
IN UINT8 Buffer[],
IN UINT16 Size,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
STATIC UINT8 PatternData[2] = {0x55, 0xAA};
LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
}
/**
* Initializer routine that will be invoked by the wrapper to initialize the input
* structure for the AllocateExecutionCache.
*
* Parameters:
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdExeAddrMapPtr Our Service interface struct
*
* @retval AGESA_SUCCESS Always Succeeds.
*
*/
AGESA_STATUS
AmdInitResetExecutionCacheAllocateInitializer (
IN AMD_CONFIG_PARAMS *StdHeader,
IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
)
{
ASSERT (AmdExeAddrMapPtr != NULL);
LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
}
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01)
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
#endif
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
AcpiCrat = AmdLateParams->AcpiCrat;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
(unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
(unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
}