/*****************************************************************************
* FUNCTION
* mau_start_monitor
* DESCRIPTION
* Configure register to set MAU assert
* a) Assert range
* b) Write and/or read transaction
* c) Physical or virtual address
* d) port mask
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* param2 : [IN] const int entry
* Index of MAU in assigned larb.
* param3 : [IN] const int rd
* 0 mean no check read transaction, and others mean check read transaction.
* param4 : [IN] const int wr
* 0 mean no check write transaction, and others mean check write transaction.
* param5 : [IN] const int vir
* 0 mean physical address, and others mean virtual address.
* param6 : [IN] const int wr
* 0 mean no check write transaction, and others mean check write transaction.
* param7 : [IN] const unsigned int start
* assert start address. (word align)
* param8 : [IN] const unsigned int end
* assert end address. (word align)
* param9 : [IN] const unsigned int port_msk
* port mask (bitwise)
* RETURNS
* None.
****************************************************************************/
static void mau_start_monitor(const int larb, const int entry, const int rd, const int wr, const int vir,
const unsigned int start, const unsigned int end, const unsigned int port_msk)
{
unsigned int regval;
unsigned int larb_base = gLarbBaseAddr[larb];
//mau entry i start address
regval = F_MAU_START_WR(wr)|F_MAU_START_RD(rd)|F_MAU_START_ADD(start);
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(entry), regval);
regval = F_MAU_END_VIR(vir)|F_MAU_END_ADD(end);
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(entry), regval);
//start monitor
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(entry));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(entry), regval|port_msk);
}
/*****************************************************************************
* FUNCTION
* mau_dump_status
* DESCRIPTION
* 1. Dump register in MAU related register.
* 2. Show MAU status
* PARAMETERS
* param1 : [IN] MTK_MAU_CONFIG* pMauConf
* MAU setting configuration.
* RETURNS
* None.
****************************************************************************/
void mau_dump_status(const int larb)
{
unsigned int larb_base;
unsigned int regval;
int i;
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
if(regval!=0)
{
SMIMSG("larb(%d), entry(%d)=========>\n", larb, i);
SMIMSG("port mask = 0x%x\n", regval);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n",
F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
}
else
{
SMIMSG("larb(%d), entry(%d) is free\n", larb, i);
}
//dump interrupt debug infomation
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
SMIMSG("violation by %s\n",smi_port_name[port]);
}
else
{
SMIMSG("no violation of entry %d\n", i);
}
#if 0
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
#endif
}
larb_clock_off(larb, "MAU");
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
return 0;
}
/*****************************************************************************
* FUNCTION
* larb_reg_restore
* DESCRIPTION
* Restore register for system resume.
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* RETURNS
* None.
****************************************************************************/
static void larb_reg_restore(const int larb)
{
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
unsigned int regval;
unsigned int larb_base = gLarbBaseAddr[larb];
//SMI registers
for(i=0; i<2; i++)
COM_WriteReg32(REG_SMI_SECUR_CON(i), *(pReg++) );
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
for(i=0; i<MAU_ENTRY_NR; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
}
/*****************************************************************************
* FUNCTION
* mau_isr
* DESCRIPTION
* 1. Print MAU status, such as port ID.
* 2. Clear interrupt status.
* PARAMETERS
* param1 : [IN] int irq
* irq number.
* param2 : [IN] void *dev_id
* No use in this function.
* RETURNS
* Type: irqreturn_t. IRQ_HANDLED mean success.
****************************************************************************/
static irqreturn_t mau_isr(int irq, void *dev_id)
{
int larb,i;
unsigned int larb_base;
unsigned int regval;
switch(irq)
{
case MT_SMI_LARB0_IRQ_ID:
larb = 0;
break;
default :
larb=0;
SMIERR("unkown irq(%d)\n",irq);
}
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
smi_aee_print("violation by %s\n",smi_port_name[port]);
}
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
}
larb_clock_off(larb, "MAU");
return IRQ_HANDLED;
}
void smi_hanging_debug(int dump_count){
// dump 5 times
int i = 0;
// Step 0 Dump register state
SMIMSG("**SMI DBG 0: Dump register state\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 1
//write SMI_LARB0+0x64 = 0
SMIMSG("**SMI DBG 1: write SMI_LARB0+0x64 = 0\n");
M4U_WriteReg32(LARB0_BASE , 0x64 , 0);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 2
//write SMI_LARB0+0x8c = 0
SMIMSG("**SMI DBG 2: write SMI_LARB0+0x8c = 0\n");
M4U_WriteReg32(LARB0_BASE , 0x8c , 0);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 3
// write SMI_LARB0+0x28 = 0x30
// write SMI_LARB0+0x24 = 0x40
SMIMSG("**SMI DBG 3: write SMI_LARB0+0x28 = 0x30, SMI_LARB0+0x24 = 0x40\n");
M4U_WriteReg32(LARB0_BASE , 0x28 ,0x30);
M4U_WriteReg32(LARB0_BASE , 0x24 ,0x40);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
// Step 4
// write 0x1400_0138 = 0xFFFF_FFFD
// write 0x1400_0138 = 0xFFFF_FFFF
SMIMSG("**SMI DBG 3: write 0x14000138 = 0xFFFFFFFD, SMI_LARB0+0x14000138 = 0xFFFFFFFF\n");
M4U_WriteReg32(0xF4000138 , 0 ,0xFFFFFFFD);
M4U_WriteReg32(0xF4000138 , 0 ,0xFFFFFFFF);
SMIMSG("==========> REG DUMP\n");
for(i=0; i<dump_count;i++){
smi_dumpCommonDebugMsg();
smi_dumpLarbDebugMsg(0);
}
}
/*****************************************************************************
* FUNCTION
* mau_disable_interrupt
* DESCRIPTION
* Configure register to disable MAU assert interrupt
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* RETURNS
* None.
****************************************************************************/
static void mau_disable_interrupt(const int larb)
{
M4U_WriteReg32(gLarbBaseAddr[larb], SMI_LARB_CON_CLR, F_SMI_LARB_CON_MAU_IRQ_EN(1));
}
int mau_disable_interrupt(int larb)
{
M4U_WriteReg32(gLarbBaseAddr[larb], SMI_LARB_CON_CLR, F_SMI_LARB_CON_MAU_IRQ_EN(1));
return 0;
}
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf , unsigned long * pu4LocalCnt)
{
int i;
unsigned long u4Concurrency = 0;
MTK_SMI_BWC_SCEN eFinalScen;
static MTK_SMI_BWC_SCEN ePreviousFinalScen = SMI_BWC_SCEN_CNT;
if((SMI_BWC_SCEN_CNT <= p_conf->scenario) || (0 > p_conf->scenario))
{
SMIERR("Incorrect SMI BWC config : 0x%x, how could this be...\n" , p_conf->scenario);
return -1;
}
//Debug - S
//SMIMSG("SMI setTo%d,%s,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , ePreviousFinalScen);
//Debug - E
spin_lock(&g_SMIInfo.SMI_lock);
if(p_conf->b_on_off)
{
//turn on certain scenario
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] += 1;
if(NULL != pu4LocalCnt)
{
pu4LocalCnt[p_conf->scenario] += 1;
}
}
else
{
//turn off certain scenario
if(0 == g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario])
{
SMIMSG("Too many turning off for global SMI profile:%d,%d\n" , p_conf->scenario , g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]);
}
else
{
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] -= 1;
}
if(NULL != pu4LocalCnt)
{
if(0 == pu4LocalCnt[p_conf->scenario])
{
SMIMSG("Process : %s did too many turning off for local SMI profile:%d,%d\n" , current->comm ,p_conf->scenario , pu4LocalCnt[p_conf->scenario]);
}
else
{
pu4LocalCnt[p_conf->scenario] -= 1;
}
}
}
for(i=0 ; i < SMI_BWC_SCEN_CNT ; i++)
{
if(g_SMIInfo.pu4ConcurrencyTable[i])
{
u4Concurrency |= (1 << i);
}
}
if((1 << SMI_BWC_SCEN_VR) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VR;
}
else if((1 << SMI_BWC_SCEN_VP) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VP;
}
else
{
eFinalScen = SMI_BWC_SCEN_NORMAL;
}
if(ePreviousFinalScen == eFinalScen)
{
SMIMSG("Scen equal%d,don't change\n" , eFinalScen);
spin_unlock(&g_SMIInfo.SMI_lock);
return 0;
}
else
{
ePreviousFinalScen = eFinalScen;
}
/*turn on larb clock*/
for( i=0 ; i < SMI_LARB_NR ; i++){
larb_clock_on(i);
}
/*Bandwidth Limiter*/
switch( eFinalScen )
{
case SMI_BWC_SCEN_VP:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VP");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x885A25);//549/4096 maximum grant counts, hard limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x6);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x2);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x3);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x3);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x2);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x4);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x2);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_VR:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VR");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0xD4F);//1359/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x884912);// 274/4096 maximum grant counts, soft limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x1);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x2);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x2);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x4);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x1);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x6);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x4);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x4);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x2);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x2);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_NORMAL:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_SCEN_NORMAL");
initSetting();
default:
break;
}
/*turn off larb clock*/
for(i = 0 ; i < SMI_LARB_NR ; i++){
larb_clock_off(i);
}
spin_unlock(&g_SMIInfo.SMI_lock);
SMIMSG("ScenTo:%d,turn %s,Curr Scen:%d,%d,%d,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , eFinalScen ,
g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VR] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VP]);
//Debug usage - S
//smi_dumpDebugMsg();
//SMIMSG("Config:%d,%d,%d\n" , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , (NULL == pu4LocalCnt ? (-1) : pu4LocalCnt[p_conf->scenario]));
//Debug usage - E
return 0;
}
//Make sure clock is on
static void initSetting(void)
{
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
// M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0);//disable BW limiter on display
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0xA11FFF);// 4096/4096 maximum grant counts, soft limiter, 8 read 8 write outstanding limit
// M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0xA11D00);// 4096/4096 maximum grant counts, soft limiter, 8 read 8 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x1);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x1);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
int retry_count = 0;
SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base);
// Write 0x60 = 0xFFFF_FFFF, enable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0xffffffff);
// Polling 0x600 = 0xaaaa
for(retry_count= 0; retry_count<64; retry_count++)
{
if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa)
{
//Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit
break;
}
SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base);
udelay(500);
}
// Write 0x60 = 0x0, disable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0x0);
// enable ISTD
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
// Show SMI always on register when larb 0 is enable
if(larb == 0){
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0));
}
return 0;
}
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf )
{
int i;
unsigned wdata = 0;
unsigned threshold = 0;
unsigned int larb_base = gLarbBaseAddr[0];
/*turn on larb clock*/
for(i=0; i<SMI_LARB_NR; i++){
larb_clock_on(i, "SMI");
}
/*Bandwidth Limiter*/
switch( p_conf->scenario )
{
#if 0
case SMI_BWC_SCEN_VP1066:
wdata = 391; //BW limit = x/4096
wdata |= (1<<11); // bw filter enable
wdata |= (1<<12); // bw hard limit enable
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
wdata = 1494; //BW limit
wdata |= (1<<11); // bw filter enable, soft mode
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x4 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 );
break;
#endif
case SMI_BWC_SCEN_VR1066:
SMIMSG("set as SMI_BWC_SCEN_VR1066");
#if 0
wdata = 432; //BW limit = x/4096
wdata |= (1<<11); // bw filter enable
wdata |= (1<<12); // bw hard limit enable
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
#else
wdata = 0;
threshold = 7;
wdata |= (1<<12); // bw hard limit enable
wdata |= (threshold<<13);
wdata |= (threshold<<18);
wdata |= (1<<23);
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );
#endif
wdata = 2026; //BW limit
wdata |= (1<<11); // bw filter enable, soft mode
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x6 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x4 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x3 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 );
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 );
/*reduce command buffer*/
//if( p_conf->b_reduce_command_buffer )
{
/*SMI COMMON reduce command buffer*/
M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0xb );
M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x323 );
M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x10c85 );
}
break;
case SMI_BWC_SCEN_NORMAL:
default:
SMIMSG("set as SMI_BWC_SCEN_NORMAL");
M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0x0 );
M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, 0x0 ); //larb0 venc:default
M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, 0x0 ); //larb1 vdec:default
{
/*SMI COMMON reduce command buffer*/
M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0x3 );
M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x320 );
M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x29ca7 );
}
break;
}
#if 0 /*dump message*/
{
#define _SMI_BC_DUMP_REG( _base_, _off_ ) \
SMIMSG( "[SMI_REG] %s + %s = 0x%08X !\n", #_base_, #_off_, M4U_ReadReg32( _base_, _off_ ) );
/*Bandwidth Limiter*/
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB0 ); //larb0 venc
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB1 ); //larb1 vdec
/*SMI COMMON reduce command buffer*/
_SMI_BC_DUMP_REG( 0x0, REG_SMI_L1LEN );
_SMI_BC_DUMP_REG( 0x0, REG_SMI_READ_FIFO_TH );
_SMI_BC_DUMP_REG( 0x0, REG_SMI_M4U_TH );
_SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_CTRL_EN);
for(i = 0; i<20; i++)
{
_SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_PORT+0x4*i);
}
/*SMI LARB reduce command buffer (RO register)*/
_SMI_BC_DUMP_REG( LARB0_BASE, 0x10 );
}
dump_smi_register();
#endif
/*turn off larb clock*/
for(i=0; i<SMI_LARB_NR; i++){
larb_clock_off(i, "SMI");
}
return 0;
}