VOID
GfxFmDisableController (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GnbLibPciRMW (
MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS),
AccessS3SaveWidth32,
0xffffffff,
1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
StdHeader
);
}
/**
* Single socket call to determine if the BIOS is responsible for updating the
* northbridge operating frequency and voltage.
*
* This function simply returns whether or not the executing core needs NB COF
* VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE BIOS needs to set up NB frequency and voltage
* @retval FALSE BIOS does not need to set up NB frequency and voltage
*
*/
BOOLEAN
GetSystemNbCofVidUpdateSingle (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN Ignored;
PCI_ADDR PciAddress;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
}
/**
* Return the number of cores (1 based count) on Node.
*
* @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
*
* @param[in] Node the Node that will be examined
* @param[in] Nb this northbridge
*
* @return the number of cores
*/
UINT8
Fam15Mod1xGetNumCoresOnNode (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Result;
UINT32 Leveling;
UINT32 Cores;
UINT8 i;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
// Read CmpCap
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_05,
REG_NB_CAPABILITY_2_5X84);
LibAmdPciReadBits (Reg, 7, 0, &Result, Nb->ConfigHandle);
// Support Downcoring
Cores = Result;
Cores++;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_DOWNCORE_3X190);
LibAmdPciReadBits (Reg, 31, 0, &Leveling, Nb->ConfigHandle);
for (i = 0; i < Cores; i++) {
if ((Leveling & ((UINT32) 1 << i)) != 0) {
Result--;
}
}
return (UINT8) (Result + 1);
}
AGESA_STATUS
STATIC
PcieMapPortsPciAddresses (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_ENGINE_CONFIG *EngineList;
AgesaStatus = AGESA_SUCCESS;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
Status = PcieFmMapPortPciAddress (EngineList);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
0,
Silicon->Address.Address.Bus,
EngineList->Type.Port.PortData.DeviceNumber,
EngineList->Type.Port.PortData.FunctionNumber,
0
);
} else {
EngineList->Type.Port.PortData.PortPresent = OFF;
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n"
);
//Report error
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
EngineList->Type.Port.PortData.DeviceNumber,
0,
0,
0,
GnbLibGetHeader (Pcie)
);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
return AgesaStatus;
}
/**
* Return the Link to the Southbridge
*
* @HtNbMethod{::F_READ_SB_LINK}
*
* @param[in] Nb this northbridge
*
* @return the Link to the southbridge
*/
UINT8
ReadSouthbridgeLink (
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
MakePciBusFromNode (0),
MakePciDeviceFromNode (0),
CPU_HTNB_FUNC_00,
REG_UNIT_ID_0X64);
LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
return (UINT8)Temp;
}
/**
* Create IVHD entry
*
*
* @param[in] Ivhd IVHD header pointer
* @param[in] StdHeader Standard configuration header
*
*/
VOID
SbCreateIvhdEntries (
OUT IVRS_IVHD_ENTRY *Ivhd,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR Start;
PCI_ADDR End;
PCI_ADDR PciAddress;
UINT32 Value;
AMD_LATE_PARAMS *LateParamsPtr;
IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n");
LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0);
// P2P alias entry
GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader);
Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0);
End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0);
GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
// HPET
GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader);
// APIC
if (LateParamsPtr->GnbLateConfiguration.FchIoapicId != 0xff) {
GnbIvhdAddSpecialDeviceEntry (
IvhdSpecialDeviceIoapic,
PciAddress,
LateParamsPtr->GnbLateConfiguration.FchIoapicId,
0xD7,
Ivhd,
StdHeader
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n");
}
AGESA_STATUS
GfxConfigPostInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GFX_PLATFORM_CONFIG *Gfx;
AMD_POST_PARAMS *PostParamsPtr;
AGESA_STATUS Status;
GNB_BUILD_OPTIONS_COMMON *GnbCommonOptions;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
ASSERT (Gfx != NULL);
if (Gfx != NULL) {
LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
GnbCommonOptions = (GNB_BUILD_OPTIONS_COMMON*) GnbFmGnbBuildOptions (StdHeader);
if (GnbBuildOptions.IgfxModeAsPcieEp) {
Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
} else {
Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
}
Gfx->StdHeader = (PVOID) StdHeader;
Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
Gfx->GmcClockGating = GnbCommonOptions->CfgGmcClockGating;
Gfx->GmcPowerGating = GnbCommonOptions->GmcPowerGating;
Gfx->UmaSteering = GnbCommonOptions->CfgUmaSteering;
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
/**
* Prepare a GNB ACG AZ Cmn entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessAcgAzCmnIndexEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
PCI_ADDR PciAddr;
CS_GNB_ACG_AZ_CMN *GnbAcgAzCmnEntry;
GnbAcgAzCmnEntry = (CS_GNB_ACG_AZ_CMN *) CurrentEntry;
if (GnbAcgAzCmnEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 9, 2, 0xE8);
PspLibPciIndirectRead (PciAddr, (UINT32) GnbAcgAzCmnEntry->Address, AccessWidth32, &GnbAcgAzCmnEntry->Value);
}
GnbAcgAzCmnEntry++;
return &GnbAcgAzCmnEntry->Header;
}
/**
* Prepare a GNB GBIF entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbGbifIndexEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
PCI_ADDR PciAddr;
CS_GNB_GBIF *GnbGbifEntry;
GnbGbifEntry = (CS_GNB_GBIF *) CurrentEntry;
if (GnbGbifEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xD0);
PspLibPciIndirectRead (PciAddr, GnbGbifEntry->Address, AccessWidth32, &GnbGbifEntry->Value);
}
GnbGbifEntry++;
return &GnbGbifEntry->Header;
}
/**
* Prepare a GNB ORB entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbOrbCfgEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
PCI_ADDR PciAddr;
CS_GNB_ORB_CFG *GnbOrbCfgEntry;
GnbOrbCfgEntry = (CS_GNB_ORB_CFG *) CurrentEntry;
if (GnbOrbCfgEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x94);
PspLibPciIndirectRead (PciAddr, (UINT32) GnbOrbCfgEntry->Address, AccessWidth32, &GnbOrbCfgEntry->Value);
}
GnbOrbCfgEntry++;
return &GnbOrbCfgEntry->Header;
}
/**
* Get CSR phy self refresh power down mode.
*
*
* @param[in] Channel DCT controller index
* @param[in] StdHeader Standard configuration header
* @retval CsrPhySrPllPdMode
*/
UINT32
GfxLibGetCsrPhySrPllPdMode (
IN UINT8 Channel,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A;
GnbLibCpuPciIndirectRead (
MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS),
D18F2x09C_x0D0FE00A_ADDRESS,
&D18F2x09C_x0D0FE00A.Value,
StdHeader
);
return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
}
/**
* Get disable DLL shutdown in self-refresh mode.
*
*
* @param[in] Channel DCT controller index
* @param[in] StdHeader Standard configuration header
* @retval DisDllShutdownSR
*/
UINT32
GfxLibGetDisDllShutdownSR (
IN UINT8 Channel,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
D18F2x90_STRUCT D18F2x090;
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS),
AccessWidth32,
&D18F2x090.Value,
StdHeader
);
return D18F2x090.Field.DisDllShutdownSR;
}
/**
* Prepare a GNB SPG CMN bits entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessSpgCmnIndexBitsEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
PCI_ADDR PciAddr;
CS_GNB_SPG_CMN_BITS *GnbSpgCmnBitsEntry;
GnbSpgCmnBitsEntry = (CS_GNB_SPG_CMN_BITS *) CurrentEntry;
if (GnbSpgCmnBitsEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 8, 0, 0xE8);
PspLibPciIndirectRead (PciAddr, (UINT32) GnbSpgCmnBitsEntry->Address, AccessWidth32, &GnbSpgCmnBitsEntry->Value);
GnbSpgCmnBitsEntry->Value &= ~GnbSpgCmnBitsEntry->Mask;
}
GnbSpgCmnBitsEntry++;
return &GnbSpgCmnBitsEntry->Header;
}
VOID
GfxFillHtcData (
IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
IN GFX_PLATFORM_CONFIG *Gfx
)
{
D18F3x64_STRUCT D18F3x64;
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS),
AccessWidth32,
&D18F3x64.Value,
GnbLibGetHeader (Gfx)
);
IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
}
/**
* Prepare a GNB miscellaneous bits entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbMiscIndexBitsEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
PCI_ADDR PciAddr;
CS_GNB_MISC_BITS *GnbMiscBitsEntry;
GnbMiscBitsEntry = (CS_GNB_MISC_BITS *) CurrentEntry;
if (GnbMiscBitsEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x60);
PspLibPciIndirectRead (PciAddr, GnbMiscBitsEntry->Address, AccessWidth32, &GnbMiscBitsEntry->Value);
GnbMiscBitsEntry->Value &= ~GnbMiscBitsEntry->Mask;
}
GnbMiscBitsEntry++;
return &GnbMiscBitsEntry->Header;
}
/**
* Turns routing tables off for a given Node
*
* @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
*
* @param[in] Node the Node that will have it's routing tables disabled
* @param[in] Nb this northbridge
*/
VOID
DisableRoutingTables (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = 1;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_INIT_CONTROL_0X6C);
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
VOID
GnbRequestVddNbPminML (
IN GNB_HANDLE *GnbHandle,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
D18F5x170_STRUCT D18F5x170;
D18F5x160_STRUCT D18F5x160;
UINT32 Millivolt;
UINT32 NbVid;
DEV_OBJECT DevObject;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminML Enter\n");
// 1) Read F5x170[NbPstateMaxVal] to find NB Pmin.
GnbRegisterReadML (GnbHandle, D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170, 0, StdHeader);
// 2) Determine voltage associated with NB Pmin. Read F5x(160+4*NbPstateMaxVal)[NbVid]. (For example, NBP0 is F5x160, NBP1 is F5x164, etc)
GnbRegisterReadML (GnbHandle, D18F5x160_TYPE, (D18F5x160_ADDRESS + (4 * D18F5x170.Field.NbPstateMaxVal)), &D18F5x160, 0, StdHeader);
NbVid = (D18F5x160.Field.NbVid_7_ << 7) | (D18F5x160.Field.NbVid_6_0_);
// 3) Make voltage request (via BIOSSMC_MSG_VDDNB_REQUEST) for voltage determined by Step 2. Note that message requires encoding in voltage, not VID.
// Use the following equation to decode SVI2 VIDs:
// Voltage = 1.55 - (0.00625*VID)
// Furthermore, VDDNB requests to SMU should be encoded in 0.25mV steps.
// Therefore, voltage should be translated into mV and then multiplied by 4, to be encoded as 0.25mV steps.
// Or... ( 1.55 * 1000 * 4) - (.00625 * 1000 * 4) * VID) = (1550 * 4) - (25 * VID)
Millivolt = (1550 * 4) - (25 * NbVid);
IDS_HDT_CONSOLE (GNB_TRACE, " Set Voltage for NbPstateMaxVal = 0x%x, Vid code 0x%x = %d mV\n", D18F5x170.Field.NbPstateMaxVal, NbVid, Millivolt);
DevObject.StdHeader = StdHeader;
DevObject.GnbHandle = GnbHandle;
DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_ENABLE_ALL_SMU_FEATURES,
VOLTAGE_CONTROLLER_MASK,
0
);
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_VDDNB_REQUEST,
Millivolt,
0
);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminML Exit\n");
return;
}
/**
* Modifies the NodeID register on the target Node
*
* @HtNbMethod{::F_WRITE_NODEID}
*
* @param[in] Node the Node that will have its NodeID altered.
* @param[in] NodeID the new value for NodeID
* @param[in] Nb this northbridge
*/
VOID
WriteNodeID (
IN UINT8 Node,
IN UINT8 NodeID,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = NodeID;
ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
/**
* Prepare a GNB device entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbDevIndexEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
UINT32 Index;
PCI_ADDR PciAddr;
CS_GNB_DEV *GnbDevEntry;
GnbDevEntry = (CS_GNB_DEV *) CurrentEntry;
if (GnbDevEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xC8);
Index = ((UINT32) GnbDevEntry->Device << 16) | (UINT32) GnbDevEntry->Address;
PspLibPciIndirectRead (PciAddr, Index, AccessWidth32, &GnbDevEntry->Value);
}
GnbDevEntry++;
return &GnbDevEntry->Header;
}
/**
* Prepare a GNB link entry on a family 15h Carrizo core.
*
* @param[in] CurrentEntry Current entry to process
*
* @return Pointer to next table entry
*/
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbLinkIndexEntry (
IN CS_RESTORATION_ENTRY_HEADER *CurrentEntry
)
{
UINT32 Index;
PCI_ADDR PciAddr;
CS_GNB_LINK *GnbLinkEntry;
GnbLinkEntry = (CS_GNB_LINK *) CurrentEntry;
if (GnbLinkEntry->Header.SaveReadValue) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
Index = (((UINT32) GnbLinkEntry->Block << 24) | ((UINT32) GnbLinkEntry->Frame << 16)) | (UINT32) GnbLinkEntry->Address;
PspLibPciIndirectRead (PciAddr, Index, AccessWidth32, &GnbLinkEntry->Value);
}
GnbLinkEntry++;
return &GnbLinkEntry->Header;
}
static void rd890_enable(device_t dev)
{
u32 address = 0;
u32 devfn;
AMD_NB_CONFIG *NbConfigPtr = NULL;
u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */
address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
NbConfigPtr = &(gConfig.Northbridges[nb_index]);
devfn = dev->path.pci.devfn;
printk(BIOS_INFO, "rd890_enable ");
printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n",
0, (devfn >> 3), (devfn & 0x07), dev->enabled);
/* we only do this once */
if(devfn==0) {
/* CIMX configuration defualt initialize */
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
if (gConfig.StandardHeader.CalloutPtr != NULL) {
gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr);
}
/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
* After this call EP are fully operational on particular NB
*/
nb_Pcie_Early_Init();
if (gConfig.StandardHeader.CalloutPtr != NULL) {
gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr);
}
nb_Early_Post_Init();
if (gConfig.StandardHeader.CalloutPtr != NULL) {
gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr);
}
nb_Mid_Post_Init();
nb_Pcie_Late_Init();
if (gConfig.StandardHeader.CalloutPtr != NULL) {
gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr);
}
nb_Late_Post_Init();
}
}
/**
* Get the quad core compute unit status for this node.
*
* @TopoNbMethod{::PF_GET_QUADCORE_COMPUTE_UNITS}
*
* @param[in] Node The node for which we want the quad core status
* @param[in] Nb Our Northbridge.
*
* @return The quad core compute unit status.
*/
UINT8
Fam16GetQuadcoreComputeUnits (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Quad;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_05,
REG_NB_COMPUTE_UNIT_5X80);
LibAmdPciReadBits (Reg, 27, 24, &Quad, Nb->ConfigHandle);
return ((UINT8) Quad);
}
VOID
PcieFmEnableSlotPowerLimit (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !Engine->Type.Port.IsSB) {
IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
(D0F0x64_x55_ADDRESS + (Engine->Type.Port.Address.Address.Device - 4) * 2) | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
0xffffffff,
1 << D0F0x64_x55_SetPowEn_OFFSET,
GnbLibGetHeader (Pcie)
);
}
}
AGESA_STATUS
GfxEnableGmmAccessV5 (
IN OUT GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 Value;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
ASSERT (GnbHandle != NULL);
// GmmBase should be 0 before enable.
ASSERT (GnbHandle->GmmBase == 0);
if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address
Gfx->GmmBase = 0;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
Gfx->GmmBase |= (Value & 0xfffffff0);
if (Gfx->GmmBase == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for FB allocated
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
if ((Value & 0xfffffff0) == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
//Push CPU MMIO pci config to S3 script
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
// Turn on memory decoding on GFX to enable access to GMM register space
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
//Push iGPU pci config to S3 script
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
GnbHandle->GmmBase = Gfx->GmmBase;
return AGESA_SUCCESS;
}
/**
* Get the dual core compute unit status for this node.
*
* @HtNbMethod{::PF_GET_DUALCORE_COMPUTE_UNITS}
*
* @param[in] Node The node for which we want the dual core status
* @param[in] Nb Our Northbridge.
*
* @return The dual core compute unit status.
*/
UINT8
Fam15Mod1xGetDualcoreComputeUnits (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Dual;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_05,
REG_NB_COMPUTE_UNIT_5X80);
LibAmdPciReadBits (Reg, 17, 16, &Dual, Nb->ConfigHandle);
return ((UINT8) Dual);
}
/**
* Writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
VOID
ModifyCurrSocketPciSingle (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR Reg;
Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
Reg.Address.Function = PciAddress->Address.Function;
Reg.Address.Register = PciAddress->Address.Register;
LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
LocalPciRegister &= Mask;
LocalPciRegister |= Data;
LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
}
/**
* Write the token stored in the scratchpad register
*
* @HtNbMethod{::F_WRITE_TOKEN}
*
* Use the CPU core count as a scratch pad.
*
* @note The location used to store the token is arbitrary. The only requirement is
* that the location warm resets to zero, and that using it will have no ill-effects
* during HyperTransport initialization.
*
* @param[in] Node the Node that marked with token
* @param[in] Value the token Value
* @param[in] Nb this northbridge
*/
VOID
WriteToken (
IN UINT8 Node,
IN UINT8 Value,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = Value;
ASSERT ((Node < MAX_NODES));
// Use CpuCnt as a scratch register
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
*
* @HtNbMethod{::F_SET_LINK_REGANG}
*
* @param[in] Node the node on which to regang a link
* @param[in] Link the sublink 0 of the sublink pair to regang
* @param[in] Nb this northbridge
*/
VOID
SetLinkRegang (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = 1;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
AGESA_STATUS
PcieFmAlibBuildAcpiTable (
IN VOID *AlibSsdtPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
D18F4x15C_STRUCT D18F4x15C;
PP_FUSE_ARRAY *PpFuseArray;
UINT32 AmlObjName;
VOID *AmlObjPtr;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n");
AgesaStatus = AGESA_SUCCESS;
// Set voltage configuration
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
GnbLibPciRead (
MAKE_SBDFO (0, 0, 0x18, 0x4, D18F4x15C_ADDRESS),
AccessWidth32,
&D18F4x15C.Value,
StdHeader
);
if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) {
// AmlObjName = 'B0DA';
AmlObjName = Int32FromChar ('A', 'D', '0', 'B');
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*) AmlObjPtr + 5) = 1;
} else {
AgesaStatus = AGESA_FATAL;
}
}
} else {
AgesaStatus = AGESA_FATAL;
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Construct a new northbridge.
*
* This routine encapsulates knowledge of how to tell significant differences between
* families of supported northbridges and what routines can be used in common and
* which are unique. A fully populated northbridge interface is provided by Nb.
*
* @param[in] Node create a northbridge interface for this Node.
* @param[in] State global state
* @param[out] Nb the caller's northbridge structure to initialize.
*/
VOID
NewNorthBridge (
IN UINT8 Node,
IN STATE_DATA *State,
OUT NORTHBRIDGE *Nb
)
{
CPU_LOGICAL_ID LogicalId;
UINT64 Match;
UINT32 RawCpuId;
PCI_ADDR Reg;
NORTHBRIDGE **InitializerInstance;
// Start with enough of the key to identify the northbridge interface
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_CPUID_3XFC);
LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle);
IDS_HDT_CONSOLE (TOPO_TRACE, "AMD Processor at Node %d has raw CPUID=%x.\n", Node, RawCpuId);
GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle);
Match = LogicalId.Family;
// Test each Northbridge interface in turn looking for a match.
// Use it to Init the Nb struct if a match is found.
//
ASSERT (OptionTopoConfiguration.TopoOptionFamilyNorthbridgeList != NULL);
InitializerInstance = (NORTHBRIDGE **) (OptionTopoConfiguration.TopoOptionFamilyNorthbridgeList);
while (*InitializerInstance != NULL) {
if ((Match & (*InitializerInstance)->CompatibleKey) != 0) {
LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle);
break;
}
InitializerInstance++;
}
// There must be an available northbridge implementation.
ASSERT (*InitializerInstance != NULL);
// Set the config handle for passing to the library.
Nb->ConfigHandle = State->ConfigHandle;
}
