}
}
return level;
}
unsigned int get_mali_max_level(void)
{
return mali_plat_data.dvfs_table_size - 1;
}
static struct resource mali_gpu_resources[] =
{
MALI_GPU_RESOURCES_MALI450_MP6_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU,
INT_MALI_PP0, INT_MALI_PP0_MMU,
INT_MALI_PP1, INT_MALI_PP1_MMU,
INT_MALI_PP2, INT_MALI_PP2_MMU,
INT_MALI_PP4, INT_MALI_PP4_MMU,
INT_MALI_PP5, INT_MALI_PP5_MMU,
INT_MALI_PP6, INT_MALI_PP6_MMU,
INT_MALI_PP)
};
static void set_limit_mali_freq(u32 idx)
{
if (mali_plat_data.limit_on == 0)
return;
if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
return;
mali_plat_data.scale_info.maxclk= idx;
revise_mali_rt();
}
void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
static u32 mali_read_phys(u32 phys_addr);
#if defined(CONFIG_ARCH_REALVIEW)
static void mali_write_phys(u32 phys_addr, u32 value);
#endif
#ifndef CONFIG_MALI_DT
static void mali_platform_device_release(struct device *device);
#if defined(CONFIG_ARCH_VEXPRESS)
#if defined(CONFIG_ARM64)
/* Juno + Mali-450 MP6 in V7 FPGA */
static struct resource mali_gpu_resources_m450_mp6[] = {
MALI_GPU_RESOURCES_MALI450_MP6_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200)
};
#else
static struct resource mali_gpu_resources_m450_mp8[] = {
MALI_GPU_RESOURCES_MALI450_MP8_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
};
static struct resource mali_gpu_resources_m450_mp6[] = {
MALI_GPU_RESOURCES_MALI450_MP6_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
};
static struct resource mali_gpu_resources_m450_mp4[] = {
MALI_GPU_RESOURCES_MALI450_MP4_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
};
#endif /* CONFIG_ARM64 */
