int arm_execute( int cycles ) { data32_t pc; data32_t insn; arm_ICount = cycles; do { #ifdef MAME_DEBUG if (mame_debug) MAME_Debug(); #endif /* load instruction */ pc = R15; insn = READ32( pc & ADDRESS_MASK ); switch (insn >> INSN_COND_SHIFT) { case COND_EQ: if (Z_IS_CLEAR(pc)) goto L_Next; break; case COND_NE: if (Z_IS_SET(pc)) goto L_Next; break; case COND_CS: if (C_IS_CLEAR(pc)) goto L_Next; break; case COND_CC: if (C_IS_SET(pc)) goto L_Next; break; case COND_MI: if (N_IS_CLEAR(pc)) goto L_Next; break; case COND_PL: if (N_IS_SET(pc)) goto L_Next; break; case COND_VS: if (V_IS_CLEAR(pc)) goto L_Next; break; case COND_VC: if (V_IS_SET(pc)) goto L_Next; break; case COND_HI: if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next; break; case COND_LS: if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next; break; case COND_GE: if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ break; case COND_LT: if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; break; case COND_GT: if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; break; case COND_LE: if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; break; case COND_NV: goto L_Next; } /* Condition satisfied, so decode the instruction */ if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */ { HandleMul(insn); R15 += 4; } else if (!(insn & 0x0c000000u)) /* Data processing */ { HandleALU(insn); } else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */ { HandleMemSingle(insn); R15 += 4; } else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */ { HandleMemBlock(insn); R15 += 4; } else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */ { HandleBranch(insn); } else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */ { pc=R15+4; R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */ SetRegister( 14, pc ); /* save PC */ R15 = (pc&PSR_MASK)|0x8|eARM_MODE_SVC|(pc&MODE_MASK); } else /* Undefined */ { logerror("%08x: Undefined instruction\n",R15); L_Next: arm_ICount -= S_CYCLE; R15 += 4; } arm_ICount -= 3; } while( arm_ICount > 0 ); return cycles - arm_ICount; } /* arm_execute */
static int h6280_execute(int cycles) { int in,lastcycle,deltacycle; h6280_ICount = cycles; /* Subtract cycles used for taking an interrupt */ h6280_ICount -= h6280.extra_cycles; h6280.extra_cycles = 0; lastcycle = h6280_ICount; /* Execute instructions */ do { h6280.ppc = h6280.pc; #ifdef MAME_DEBUG { if (mame_debug) { /* Copy the segmentation registers for debugger to use */ int i; for (i=0; i<8; i++) H6280_debug_mmr[i]=h6280.mmr[i]; MAME_Debug(); } } #endif /* Execute 1 instruction */ in=RDOP(); PCW++; insnh6280[in](); /* Check internal timer */ if(h6280.timer_status) { deltacycle = lastcycle - h6280_ICount; h6280.timer_value -= deltacycle; if(h6280.timer_value<=0 && h6280.timer_ack==1) { h6280.timer_ack=h6280.timer_status=0; set_irq_line(2,ASSERT_LINE); } } lastcycle = h6280_ICount; /* If PC has not changed we are stuck in a tight loop, may as well finish */ if( h6280.pc.d == h6280.ppc.d ) { if (h6280_ICount > 0) h6280_ICount=0; h6280.extra_cycles = 0; return cycles; } } while (h6280_ICount > 0); /* Subtract cycles used for taking an interrupt */ h6280_ICount -= h6280.extra_cycles; h6280.extra_cycles = 0; return cycles - h6280_ICount; }