/*!
\brief This function registers an interrupt in NVIC table
The sync object is used for synchronization between different thread or ISR and
a thread.
\param iIntrNum - Interrupt number to register
\param pEntry - Pointer to the interrupt handler
\param ucPriority - priority of the interrupt
\return upon successful creation the function should return 0
Otherwise, a negative value indicating the error code shall be returned
\note
\warning
*/
OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority)
{
MAP_IntRegister(iIntrNum,(void(*)(void))pEntry);
MAP_IntPrioritySet(iIntrNum, ucPriority);
MAP_IntEnable(iIntrNum);
return OSI_OK;
}
bool mgos_uart_hal_init(struct mgos_uart_state *us) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
uint32_t periph, int_no;
void (*int_handler)();
/* TODO(rojer): Configurable pin mappings? */
if (us->uart_no == 0) {
periph = PRCM_UARTA0;
int_no = INT_UARTA0;
int_handler = u0_int;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (us->uart_no == 1) {
periph = PRCM_UARTA1;
int_no = INT_UARTA1;
int_handler = u1_int;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return false;
}
struct cc32xx_uart_state *ds =
(struct cc32xx_uart_state *) calloc(1, sizeof(*ds));
ds->base = base;
cs_rbuf_init(&ds->isr_rx_buf, CC32xx_UART_ISR_RX_BUF_SIZE);
us->dev_data = ds;
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
MAP_IntRegister(int_no, int_handler);
MAP_IntPrioritySet(int_no, INT_PRIORITY_LVL_1);
MAP_IntEnable(int_no);
return true;
}
int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue
{
if(InterruptHdl == NULL)
{
//De-register Interprocessor communication interrupt between App and NWP
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_NWPIC);
#else
MAP_IntDisable(INT_NWPIC);
MAP_IntUnregister(INT_NWPIC);
MAP_IntPendClear(INT_NWPIC);
#endif
}
else
{
#ifdef SL_PLATFORM_MULTI_THREADED
MAP_IntPendClear(INT_NWPIC);
osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl,
INT_PRIORITY_LVL_1);
#else
MAP_IntRegister(INT_NWPIC, InterruptHdl);
MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
MAP_IntPendClear(INT_NWPIC);
MAP_IntEnable(INT_NWPIC);
#endif
}
return 0;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
unsigned long ulSpiBitRate;
tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR);
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
MAP_SPICSDisable(ulBase);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
//
// Configure SPI interface
//
if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 )
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32)
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33)
{
ulSpiBitRate = SPI_RATE_20M;
}
MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaEnable(ulBase,SPI_RX_DMA);
MAP_SPIDmaEnable(ulBase,SPI_TX_DMA);
MAP_SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
MAP_IntEnable(INT_LSPI);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
MAP_SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
