static void intel_mid_arch_setup(void) { if (boot_cpu_data.x86 != 6) { pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; goto out; } switch (boot_cpu_data.x86_model) { case 0x35: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; break; case 0x3C: case 0x4A: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; break; case 0x27: default: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; break; } if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); else { intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); pr_info("ARCH: Unknown SoC, assuming PENWELL!\n"); } out: if (intel_mid_ops->arch_setup) intel_mid_ops->arch_setup(); }
static void __cpuinit intel_mid_arch_setup(void) { if (boot_cpu_data.x86 != 6) { pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; return; } switch (boot_cpu_data.x86_model) { case 0x5A: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_ANNIEDALE; break; case 0x27: default: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; break; } if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); else { intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); pr_info("ARCH: Uknown SoC, assuming PENWELL!\n"); } if (intel_mid_ops->arch_setup) intel_mid_ops->arch_setup(); }
static void intel_mid_arch_setup(void) { if (boot_cpu_data.x86 != 6) { pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; goto out; } switch (boot_cpu_data.x86_model) { case 0x35: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; break; case 0x3C: case 0x4A: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; break; case 0x27: default: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; break; } if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); else { intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); pr_info("ARCH: Unknown SoC, assuming Penwell!\n"); } out: if (intel_mid_ops->arch_setup) intel_mid_ops->arch_setup(); /* * Intel MID platforms are using explicitly defined regulators. * * Let the regulator core know that we do not have any additional * regulators left. This lets it substitute unprovided regulators with * dummy ones: */ regulator_has_full_constraints(); }