void pll_init(void)
{
/* The PLL pre-divider affects this!!!
* Multiply 48Mhz reference crystal /CCHR by 10 to achieve system clock of 80Mhz
*/
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
void
pll_init()
{
/*
* Multiply 8Mhz reference crystal by 8 to acheive system clock of 64Mhz
*/
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2);
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
static void pll_init(void)
{
MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 48MHz / 6 = 8MHz
/* The PLL pre-divider affects this!!!
* Multiply 8Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
*/
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK)) {
}
}
void
pll_init(void)
{
//MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 25MHz / 5 = 5MHz
/* The PLL pre-divider affects this!!!
* Multiply 25Mhz reference crystal /CCHR by 12 to acheive system clock of 60Mhz
*/
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
void pll_init_128M(void)
{
//fsys 计数公式：fsys = fref × 2 × (MFD + 2) ÷ (2 ^ RFD);
//fref 计算公式：fref= fosc / (CCHR+1);
//MCF_CLOCK_CCHR 默认值为5
//MFD=6,RFD=0。系统频率计算：
//fsys=48MHz / (CCHR+1) × 2 × (MFD + 2) ÷ (2^RFD) = 128Mhz.
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(6)
| MCF_CLOCK_SYNCR_RFD(0)
| MCF_CLOCK_SYNCR_CLKSRC
| MCF_CLOCK_SYNCR_PLLMODE
| MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK)) //等待锁相环锁定
{
}
}
void
mcf5225x_pll_init(void)
{
/*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
#ifndef OMIT_OCLR_CONFIGURATION
MCF_CLOCK_OCLR = 0xC0; //turn on crystal
MCF_CLOCK_CCLR = 0x00; //switch to crystal
MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
#endif
/* The PLL pre divider - 48MHz / 6 = 8MHz */
MCF_CLOCK_CCHR =0x05;
/* The PLL pre-divider affects this!!!
* Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
*/
MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
//80
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
//64
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
//16
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
//8
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
//1
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
/* Initialize FLASHBAR (0x00) */
asm volatile(
"move.l #0x00,%d0 \n"
"andi.l #0xFFF80000,%d0 \n"
"add.l #0x41,%d0 \n"
"movec %d0,%FLASHBAR "
);
portDISABLE_INTERRUPTS();
/* RAMBAR. */
MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;
/* Multiply 25MHz crystal by 12 to get 60MHz clock. */
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
/* Setup the port used to toggle LEDs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
{
/* This will get called if a stack overflow is detected during the context
switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack
problems within nested interrupts, but only do this for debug purposes as
it will increase the context switch time. */