/*
* Description:
* This function will prepare message pools for the Thunderbolt controller
* Arguments:
* DevExt - HBA miniport driver's adapter data storage structure
* pMemLocation - start of the memory allocated for Thunderbolt.
* Return Value:
* TRUE if successful
* FALSE if failed
*/
int
mfi_tbolt_init_desc_pool(struct mfi_softc *sc, uint8_t* mem_location,
uint32_t tbolt_contg_length)
{
uint32_t offset = 0;
uint8_t *addr = mem_location;
/* Request Descriptor Base physical Address */
/* For Request Decriptors Virtual Memory */
/* Initialise the aligned IO Frames Virtual Memory Pointer */
if (((uintptr_t)addr) & (0xFF)) {
addr = &addr[sc->raid_io_msg_size];
addr = (uint8_t *)((uintptr_t)addr & (~0xFF));
sc->request_message_pool_align = addr;
} else
sc->request_message_pool_align = addr;
offset = sc->request_message_pool_align - sc->request_message_pool;
sc->request_msg_busaddr = sc->mfi_tb_busaddr + offset;
/* DJA XXX should this be bus dma ??? */
/* Skip request message pool */
addr = &addr[sc->raid_io_msg_size * (sc->mfi_max_fw_cmds + 1)];
/* Reply Frame Pool is initialized */
sc->reply_frame_pool = (struct mfi_mpi2_reply_header *) addr;
if (((uintptr_t)addr) & (0xFF)) {
addr = &addr[sc->reply_size];
addr = (uint8_t *)((uintptr_t)addr & (~0xFF));
}
sc->reply_frame_pool_align
= (struct mfi_mpi2_reply_header *)addr;
offset = (uintptr_t)sc->reply_frame_pool_align
- (uintptr_t)sc->request_message_pool;
sc->reply_frame_busaddr = sc->mfi_tb_busaddr + offset;
/* Skip Reply Frame Pool */
addr += sc->reply_size * sc->mfi_max_fw_cmds;
sc->reply_pool_limit = addr;
/* initializing reply address to 0xFFFFFFFF */
memset((uint8_t *)sc->reply_frame_pool, 0xFF,
(sc->reply_size * sc->mfi_max_fw_cmds));
offset = sc->reply_size * sc->mfi_max_fw_cmds;
sc->sg_frame_busaddr = sc->reply_frame_busaddr + offset;
/* initialize the last_reply_idx to 0 */
sc->last_reply_idx = 0;
MFI_WRITE4(sc, MFI_RFPI, sc->mfi_max_fw_cmds - 1);
MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
offset = (sc->sg_frame_busaddr + (MEGASAS_MAX_SZ_CHAIN_FRAME *
sc->mfi_max_fw_cmds)) - sc->mfi_tb_busaddr;
if (offset > tbolt_contg_length)
device_printf(sc->mfi_dev, "Error:Initialized more than "
"allocated\n");
return 0;
}
void
mfi_tbolt_issue_cmd_ppc(struct mfi_softc *sc, bus_addr_t bus_add,
uint32_t frame_cnt)
{
bus_add |= (MFI_REQ_DESCRIPT_FLAGS_MFA
<< MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
MFI_WRITE4(sc, MFI_IQPL, (uint32_t)bus_add);
MFI_WRITE4(sc, MFI_IQPH, (uint32_t)((uint64_t)bus_add >> 32));
}
/*
* mfi_tbolt_adp_reset - For controller reset
* @regs: MFI register set
*/
int
mfi_tbolt_adp_reset(struct mfi_softc *sc)
{
int retry = 0, i = 0;
int HostDiag;
MFI_WRITE4(sc, MFI_WSR, 0xF);
MFI_WRITE4(sc, MFI_WSR, 4);
MFI_WRITE4(sc, MFI_WSR, 0xB);
MFI_WRITE4(sc, MFI_WSR, 2);
MFI_WRITE4(sc, MFI_WSR, 7);
MFI_WRITE4(sc, MFI_WSR, 0xD);
for (i = 0; i < 10000; i++) ;
HostDiag = (uint32_t)MFI_READ4(sc, MFI_HDR);
while (!( HostDiag & DIAG_WRITE_ENABLE)) {
for (i = 0; i < 1000; i++);
HostDiag = (uint32_t)MFI_READ4(sc, MFI_HDR);
device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: retry time=%d, "
"hostdiag=%#x\n", retry, HostDiag);
if (retry++ >= 100)
return 1;
}
device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: HostDiag=%#x\n", HostDiag);
MFI_WRITE4(sc, MFI_HDR, (HostDiag | DIAG_RESET_ADAPTER));
for (i=0; i < 10; i++) {
for (i = 0; i < 10000; i++);
}
HostDiag = (uint32_t)MFI_READ4(sc, MFI_RSR);
while (HostDiag & DIAG_RESET_ADAPTER) {
for (i = 0; i < 1000; i++) ;
HostDiag = (uint32_t)MFI_READ4(sc, MFI_RSR);
device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: retry time=%d, "
"hostdiag=%#x\n", retry, HostDiag);
if (retry++ >= 1000)
return 1;
}
return 0;
}
int32_t
mfi_tbolt_check_clear_intr_ppc(struct mfi_softc *sc)
{
int32_t status, mfi_status = 0;
status = MFI_READ4(sc, MFI_OSTS);
if (status & 1) {
MFI_WRITE4(sc, MFI_OSTS, status);
MFI_READ4(sc, MFI_OSTS);
if (status & MFI_STATE_CHANGE_INTERRUPT) {
mfi_status |= MFI_FIRMWARE_STATE_CHANGE;
}
return mfi_status;
}
if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK))
return 1;
MFI_READ4(sc, MFI_OSTS);
return 0;
}
void
mfi_tbolt_disable_intr_ppc(struct mfi_softc *sc)
{
MFI_WRITE4(sc, MFI_OMSK, 0xFFFFFFFF);
MFI_READ4(sc, MFI_OMSK);
}
void
mfi_tbolt_enable_intr_ppc(struct mfi_softc *sc)
{
MFI_WRITE4(sc, MFI_OMSK, ~MFI_FUSION_ENABLE_INTERRUPT_MASK);
MFI_READ4(sc, MFI_OMSK);
}
