static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t val;
struct i2c_client *client = mhl_ctrl->i2c_handle;
pr_debug("%s: cur st [0x%x]\n", __func__,
mhl_ctrl->cur_state);
if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
/* Already in D0 - MHL power state */
pr_err("%s: cur st not D0\n", __func__);
return;
}
/* spin_lock_irqsave(&mhl_state_lock, flags); */
switch_mode(mhl_ctrl, POWER_STATE_D0_MHL);
/* spin_unlock_irqrestore(&mhl_state_lock, flags); */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
MHL_SII_CBUS_WR(0x07, 0xF2);
/*
* Keep the discovery enabled. Need RGND interrupt
* Possibly chip disables discovery after MHL_EST??
* Need to re-enable here
*/
val = MHL_SII_PAGE3_RD(0x10);
MHL_SII_PAGE3_WR(0x10, val | BIT0);
return;
}
static void cbus_reset(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t i;
struct i2c_client *client = mhl_ctrl->i2c_handle;
/*
* REG_SRST
*/
MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, BIT3);
msleep(20);
MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, 0x00);
/*
* REG_INTR1 and REG_INTR4
*/
MHL_SII_REG_NAME_WR(REG_INTR1_MASK, BIT6);
MHL_SII_REG_NAME_WR(REG_INTR4_MASK,
BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
if (mhl_ctrl->chip_rev_id < 1)
MHL_SII_REG_NAME_WR(REG_INTR5_MASK, BIT3 | BIT4);
else
MHL_SII_REG_NAME_WR(REG_INTR5_MASK, 0x00);
/* Unmask CBUS1 Intrs */
MHL_SII_REG_NAME_WR(REG_CBUS_INTR_ENABLE,
BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
/* Unmask CBUS2 Intrs */
MHL_SII_REG_NAME_WR(REG_CBUS_MSC_INT2_ENABLE, BIT2 | BIT3);
for (i = 0; i < 4; i++) {
/*
* Enable WRITE_STAT interrupt for writes to
* all 4 MSC Status registers.
*/
MHL_SII_CBUS_WR((0xE0 + i), 0xFF);
/*
* Enable SET_INT interrupt for writes to
* all 4 MSC Interrupt registers.
*/
MHL_SII_CBUS_WR((0xF0 + i), 0xFF);
}
}
static void cbus_reset(struct i2c_client *client)
{
uint8_t i;
/*
* REG_SRST
*/
MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, BIT3);
msleep(20);
MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, 0x00);
/*
* REG_INTR1 and REG_INTR4
*/
MHL_SII_REG_NAME_WR(REG_INTR1_MASK, BIT6);
MHL_SII_REG_NAME_WR(REG_INTR4_MASK,
BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
MHL_SII_REG_NAME_WR(REG_INTR5_MASK, 0x00);
/* Unmask CBUS1 Intrs */
MHL_SII_CBUS_WR(0x0009,
BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
/* Unmask CBUS2 Intrs */
MHL_SII_CBUS_WR(0x001F, BIT2 | BIT3);
for (i = 0; i < 4; i++) {
/*
* Enable WRITE_STAT interrupt for writes to
* all 4 MSC Status registers.
*/
MHL_SII_CBUS_WR((0xE0 + i), 0xFF);
/*
* Enable SET_INT interrupt for writes to
* all 4 MSC Interrupt registers.
*/
MHL_SII_CBUS_WR((0xF0 + i), 0xFF);
}
return;
}
static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t val;
struct i2c_client *client = mhl_ctrl->i2c_handle;
pr_debug("%s: cur st [0x%x]\n", __func__,
mhl_ctrl->cur_state);
if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
/* Already in D0 - MHL power state */
pr_err("%s: cur st not D0\n", __func__);
return;
}
switch_mode(mhl_ctrl, POWER_STATE_D0_MHL, true);
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
MHL_SII_CBUS_WR(0x07, 0xF2);
/*
* Keep the discovery enabled. Need RGND interrupt
* Possibly chip disables discovery after MHL_EST??
* Need to re-enable here
*/
val = MHL_SII_PAGE3_RD(0x10);
MHL_SII_PAGE3_WR(0x10, val | BIT0);
/*
* indicate DCAP_RDY and DCAP_CHG
* to the peer only after
* msm conn has been established
*/
mhl_msc_send_write_stat(mhl_ctrl,
MHL_STATUS_REG_CONNECTED_RDY,
MHL_STATUS_DCAP_RDY);
mhl_msc_send_set_int(mhl_ctrl,
MHL_RCHANGE_INT,
MHL_INT_DCAP_CHG,
MSC_PRIORITY_SEND);
}
static void init_cbus_regs(struct i2c_client *client)
{
uint8_t regval;
/* Increase DDC translation layer timer*/
MHL_SII_CBUS_WR(0x0007, 0xF2);
/* Drive High Time */
MHL_SII_CBUS_WR(0x0036, 0x0B);
/* Use programmed timing */
MHL_SII_CBUS_WR(0x0039, 0x30);
/* CBUS Drive Strength */
MHL_SII_CBUS_WR(0x0040, 0x03);
/*
* Write initial default settings
* to devcap regs: default settings
*/
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_DEV_STATE, DEVCAP_VAL_DEV_STATE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_MHL_VERSION, DEVCAP_VAL_MHL_VERSION);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_DEV_CAT, DEVCAP_VAL_DEV_CAT);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_ADOPTER_ID_H, DEVCAP_VAL_ADOPTER_ID_H);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_ADOPTER_ID_L, DEVCAP_VAL_ADOPTER_ID_L);
MHL_SII_CBUS_WR(0x0080 | DEVCAP_OFFSET_VID_LINK_MODE,
DEVCAP_VAL_VID_LINK_MODE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_AUD_LINK_MODE,
DEVCAP_VAL_AUD_LINK_MODE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_VIDEO_TYPE, DEVCAP_VAL_VIDEO_TYPE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_LOG_DEV_MAP, DEVCAP_VAL_LOG_DEV_MAP);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_BANDWIDTH, DEVCAP_VAL_BANDWIDTH);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_FEATURE_FLAG, DEVCAP_VAL_FEATURE_FLAG);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_DEVICE_ID_H, DEVCAP_VAL_DEVICE_ID_H);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_DEVICE_ID_L, DEVCAP_VAL_DEVICE_ID_L);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_SCRATCHPAD_SIZE,
DEVCAP_VAL_SCRATCHPAD_SIZE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_INT_STAT_SIZE,
DEVCAP_VAL_INT_STAT_SIZE);
MHL_SII_CBUS_WR(0x0080 |
DEVCAP_OFFSET_RESERVED, DEVCAP_VAL_RESERVED);
/* Make bits 2,3 (initiator timeout) to 1,1
* for register CBUS_LINK_CONTROL_2
* REG_CBUS_LINK_CONTROL_2
*/
regval = MHL_SII_CBUS_RD(0x0031);
regval = (regval | 0x0C);
/* REG_CBUS_LINK_CONTROL_2 */
MHL_SII_CBUS_WR(0x0031, regval);
/* REG_MSC_TIMEOUT_LIMIT */
MHL_SII_CBUS_WR(0x0022, 0x0F);
/* REG_CBUS_LINK_CONTROL_1 */
MHL_SII_CBUS_WR(0x0030, 0x01);
/* disallow vendor specific commands */
MHL_SII_CBUS_MOD(0x002E, BIT4, BIT4);
}
static void clear_all_intrs(struct i2c_client *client)
{
uint8_t regval = 0x00;
pr_debug_intr("********* exiting isr mask check ?? *************\n");
pr_debug_intr("int1 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR1));
pr_debug_intr("int3 mask = %02X\n",
(int) MHL_SII_PAGE0_RD(0x0077));
pr_debug_intr("int4 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR4));
pr_debug_intr("int5 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR5));
pr_debug_intr("cbus1 mask = %02X\n",
(int) MHL_SII_CBUS_RD(0x0009));
pr_debug_intr("cbus2 mask = %02X\n",
(int) MHL_SII_CBUS_RD(0x001F));
pr_debug_intr("********* end of isr mask check *************\n");
regval = MHL_SII_REG_NAME_RD(REG_INTR1);
pr_debug_intr("int1 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR1, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR2);
pr_debug_intr("int2 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR2, regval);
regval = MHL_SII_PAGE0_RD(0x0073);
pr_debug_intr("int3 st = %02X\n", (int)regval);
MHL_SII_PAGE0_WR(0x0073, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR4);
pr_debug_intr("int4 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR4, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR5);
pr_debug_intr("int5 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR5, regval);
regval = MHL_SII_CBUS_RD(0x0008);
pr_debug_intr("cbusInt st = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x0008, regval);
regval = MHL_SII_CBUS_RD(0x001E);
pr_debug_intr("CBUS intR_2: %d\n", (int)regval);
MHL_SII_CBUS_WR(0x001E, regval);
regval = MHL_SII_CBUS_RD(0x00A0);
pr_debug_intr("A0 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A0, regval);
regval = MHL_SII_CBUS_RD(0x00A1);
pr_debug_intr("A1 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A1, regval);
regval = MHL_SII_CBUS_RD(0x00A2);
pr_debug_intr("A2 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A2, regval);
regval = MHL_SII_CBUS_RD(0x00A3);
pr_debug_intr("A3 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A3, regval);
regval = MHL_SII_CBUS_RD(0x00B0);
pr_debug_intr("B0 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B0, regval);
regval = MHL_SII_CBUS_RD(0x00B1);
pr_debug_intr("B1 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B1, regval);
regval = MHL_SII_CBUS_RD(0x00B2);
pr_debug_intr("B2 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B2, regval);
regval = MHL_SII_CBUS_RD(0x00B3);
pr_debug_intr("B3 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B3, regval);
regval = MHL_SII_CBUS_RD(0x00E0);
pr_debug_intr("E0 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E0, regval);
regval = MHL_SII_CBUS_RD(0x00E1);
pr_debug_intr("E1 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E1, regval);
regval = MHL_SII_CBUS_RD(0x00E2);
pr_debug_intr("E2 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E2, regval);
regval = MHL_SII_CBUS_RD(0x00E3);
pr_debug_intr("E3 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E3, regval);
regval = MHL_SII_CBUS_RD(0x00F0);
pr_debug_intr("F0 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F0, regval);
regval = MHL_SII_CBUS_RD(0x00F1);
pr_debug_intr("F1 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F1, regval);
regval = MHL_SII_CBUS_RD(0x00F2);
pr_debug_intr("F2 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F2, regval);
regval = MHL_SII_CBUS_RD(0x00F3);
pr_debug_intr("F3 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F3, regval);
pr_debug_intr("********* end of exiting in isr *************\n");
}
