static void owl_mdio_write(struct eth_device *dev,uint8_t phyreg, uint16_t phydata)
{
struct owl_mac_info *owl_info = dev->priv;
int phyaddr = owl_info->phy_addr;
u32 op_reg;
do {
op_reg = readl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
writel(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_WRITE) | MII_MNG_REGADD(phyreg) | MII_MNG_PHYADD(phyaddr) | phydata, MAC_CSR10);
do{
op_reg = readl(MAC_CSR10);
}while(op_reg & MII_MNG_SB);
}
/**
* write_phy_reg - MII interface to write @val to @reg_addr register of phy at @phy_addr
* return zero if success, negative value if fail
* may be used by other standard ethernet phy
*/
int write_phy_reg_ksz8041(ec_priv_t * ecp, unsigned short reg_addr, unsigned short val)
{
u32 op_reg;
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
putl(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_WRITE) | MII_MNG_REGADD(reg_addr) |
MII_MNG_PHYADD(ASOC_ETHERNET_PHY_ADDR) | val, MAC_CSR10);
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
return 0;
}
/**
* read_phy_reg - MII interface to read @reg_addr register of phy at @phy_addr
* return positive and zero value if success, or negative value if fail
* may be used by other standard ethernet phy
*/
unsigned short read_phy_reg_ksz8041(ec_priv_t * ecp, unsigned short reg_addr)
{
u32 op_reg;
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
putl(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_READ) | MII_MNG_REGADD(reg_addr) |
MII_MNG_PHYADD(ASOC_ETHERNET_PHY_ADDR), MAC_CSR10);
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
return (u16)MII_MNG_DATA(op_reg);
}
static int owl_mac_hardware_init(struct eth_device *dev)
{
struct owl_mac_info *owl_info = dev->priv;
int tmp = 0;
//u32 reg_val = 0;
owl_mac_clock_enable(dev);
/* hardware soft reset, and set bus mode */
writel(readl(MAC_CSR0) | EC_BMODE_SWR, MAC_CSR0);
do{
udelay(10);
if(tmp++ > OWL_MAC_SWRESET_TIMEOUT)
break;
}while(readl(MAC_CSR0) & EC_BMODE_SWR);
if(tmp > OWL_MAC_SWRESET_TIMEOUT)
printf("warning:MAC reset error 0x%x\n",readl(MAC_CSR0));
writel(readl(MAC_CTRL) & (~(EC_MACCTRL_RSIS)), MAC_CTRL);
writel(readl(MAC_CTRL) & (~(EC_MACCTRL_RCPS)), MAC_CTRL);
writel((readl(MAC_CSR10) & REG_CLEAR)| MII_MNG_OPCODE(MII_OP_CDS), MAC_CSR10);
writel(owl_info->rx_bd_paddr, MAC_CSR3);
writel(owl_info->tx_bd_paddr, MAC_CSR4);
writel(readl(MAC_CSR6) | EC_OPMODE_FD | EC_OPMODE_SPEED(0), MAC_CSR6);
writel(readl(MAC_CSR6) & ~EC_OPMODE_PR, MAC_CSR6);
writel(0x004e0000, MAC_CSR11);
/* Reset the phy */
//writel(readl(GPIO_COUTEN) | (0x1 << OWL_MAC_PHY_POWER) ,GPIO_COUTEN);
//writel(readl(GPIO_CDAT) | (0x1 << OWL_MAC_PHY_POWER) ,GPIO_CDAT);
//writel(readl(GPIO_COUTEN) | (0x1 << OWL_MAC_PHY_RESET) ,GPIO_COUTEN);
//writel(readl(GPIO_CDAT) | (0x0 << OWL_MAC_PHY_RESET) ,GPIO_CDAT);
//mdelay(20);
//writel(readl(GPIO_CDAT) | (0x1 << OWL_MAC_PHY_RESET) ,GPIO_CDAT);
//mdelay(10);
//owl_mac_activate_gpio(&owl_info->phy_power_gpio);
//udelay(100);
owl_mac_power_on(dev);
owl_mac_phy_reset(dev);
return 0;
}
static uint16_t owl_mdio_read(struct eth_device *dev, uint8_t phyreg)
{
struct owl_mac_info *owl_info = dev->priv;
int phyaddr = owl_info->phy_addr;
u32 op_reg;
do{
op_reg = readl(MAC_CSR10);
}while(op_reg & MII_MNG_SB);
writel(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_READ) | MII_MNG_REGADD(phyreg) | MII_MNG_PHYADD(phyaddr), MAC_CSR10);
do{
op_reg = readl(MAC_CSR10);
}while(op_reg & MII_MNG_SB);
return (uint16_t)MII_MNG_DATA(op_reg);
}
/**
* read_phy_reg - MII interface to read @reg_addr register of phy at @phy_addr
* return positive and zero value if success, or negative value if fail
* may be used by other standard ethernet phy
*/
unsigned short read_phy_reg_sr8201g(ec_priv_t * ecp, unsigned short reg_addr)
{
u32 op_reg;
u32 phy_addr;
if((ecp->phy_addr)!=0xFF)
phy_addr=ecp->phy_addr;
else
phy_addr=ASOC_ETHERNET_PHY_ADDR;
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
putl(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_READ) | MII_MNG_REGADD(reg_addr) |
MII_MNG_PHYADD(phy_addr), MAC_CSR10);
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
return (u16)MII_MNG_DATA(op_reg);
}
/**
* write_phy_reg - MII interface to write @val to @reg_addr register of phy at @phy_addr
* return zero if success, negative value if fail
* may be used by other standard ethernet phy
*/
int write_phy_reg_sr8201g(ec_priv_t * ecp, unsigned short reg_addr, unsigned short val)
{
u32 op_reg;
u32 phy_addr;
if((ecp->phy_addr)!=0xFF)
phy_addr=ecp->phy_addr;
else
phy_addr=ASOC_ETHERNET_PHY_ADDR;
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
putl(MII_MNG_SB | MII_MNG_OPCODE(MII_OP_WRITE) | MII_MNG_REGADD(reg_addr) |
MII_MNG_PHYADD(phy_addr) | val, MAC_CSR10);
do {
op_reg = getl(MAC_CSR10);
} while (op_reg & MII_MNG_SB);
return 0;
}
