t_nmf_error METH(construct)(void)
{
t_uint16 i;
//t1xhv_remap_interrupts();
// IT 2, 11 (HW sem), 20, 31 (stack checker) not to be touched
// ITREMAP_interf_reg20 = 42; /* 20) VPP_SYNC\n */
/* unmask all Interrupts */
MMDSP_EMU_MASKIT(INTERRUPT_ENABLE);
/* only unmask the interrupts needed for video !
don't touch other interrupts otherwise we get problems
when running with other medias on SVA */
ITREMAP_interf_itmskl &= (0xFFFFU^(1U<<12));
ITREMAP_interf_itmskh &= (0xFFFFU^(1U<<(21-16))^(1U<<(26-16)));
#ifdef __ndk8500_a0__
ITREMAP_interf_itmskh &= (0xFFFFU^(1U<<(22-16)));
#endif
// oldITREMAP_interf_reg12 = ITREMAP_interf_reg12;
ITREMAP_interf_reg12 = 39;
// oldITREMAP_interf_reg21 = ITREMAP_interf_reg21;
ITREMAP_interf_reg21 = 41;
// oldITREMAP_interf_reg26 = ITREMAP_interf_reg26;
ITREMAP_interf_reg26 = 43;
#ifdef __ndk8500_a0__
ITREMAP_interf_reg22 = 45; /* CABAC interrupt */
ITREMAP_interf_reg30 = 62; /* ITC_CMP3 (for watchdog based on SVA timer) */
#endif
for (i=0; i<NB_INTERRUPT; i++) {
interrupt_desc[i].registered = FALSE;
}
return NMF_OK;
} /* end of construct() function */
void mtf_read_table(t_uint32 addr_in,t_uint16 *pt_dest,t_uint16 len,
t_uint16 incr,t_mtf_swap_cfg swap_cfg)
{
/* this version does not handle unaligned addr_in */
/* Only FIFO 16 is used */
t_uint16 EMU_unit_maskit_prev; /* current value of EMU_unit_maskit */
volatile __XIO t_uint16 *ptr_mtf_r = 0;
t_uint16 value;
t_uint16 current_length1 = len;
t_uint16 current_length2 = (8-(len%8))%8;
t_uint16 tfl;
t_uint32 read_value=0;
t_uint32 read_value_32 = 0;
t_uint16 pgm_dma_swap = 0;
/* start of critical code section*/
EMU_unit_maskit_prev = EMU_unit_maskit;
MMDSP_EMU_MASKIT(INTERRUPT_DISABLE);
/* Check that transfer is completed */
#ifdef T1XHV_SIA
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_R) != 0);
#else
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_R) != 0);
#endif
/* configure swap in DMA and MTF */
switch (swap_cfg)
{
case MTF_NO_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16);
break;
case MTF_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16_SWAP);
break;
case MTF_NO_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16);
break;
case MTF_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16_SWAP);
break;
default:
ASSERT(0);
/* other not possible */
break;
}
#ifdef T1XHV_SIA
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_R)|(pgm_dma_swap ? MTF_R : 0));
#else
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_R)|(pgm_dma_swap ? MTF_R : 0));
#endif
/* program DMA transfer */
tfl = (current_length2 + current_length1) >>2;
/* Len is 16 bit word, tfl is 64 bit word */
/* addr in must be aligned on 64 bits */
DMA_SET_MTF_READ_PARAM((addr_in&(~0x7UL)),incr,tfl);
/* start DMA transfer */
#ifdef T1XHV_SIA
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_R);
MTF_SET_REG(MTF_R_REG_ENR,0x1);
#else
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_R);
MTF_SET_REG(MTF_R_REG_ENR,0x1);
#endif
/* get all values from MTF_R Fifo */
while (current_length1--) {
value = *ptr_mtf_r; /* read from fifo */
*pt_dest++ = value; /* write to MMDSP table */
}
/* Flush the Fifo */
while (current_length2--) {
value = *ptr_mtf_r; /* read from fifo */
}
/* MTF_SET_REG(MTF_R_REG_DIR,0x1);*/
/*DMA_SET_REG(DMA_DIR_L,MTF_R);*/ /* removed according to latest HW spec */
/* end of critical code section */
/* if we were in a critical code section before this function, we remain critical*/
MMDSP_EMU_MASKIT(EMU_unit_maskit_prev);
}
void mtf_write_table(t_uint32 addr_out,t_uint16 *pt_src,t_uint16 len,
t_uint16 incr,t_mtf_swap_cfg swap_cfg)
{
t_uint16 EMU_unit_maskit_prev; /* current value of EMU_unit_maskit */
volatile __XIO t_uint16 *ptr_mtf_w = 0;
t_uint16 value;
t_uint32 read_value=0;
t_uint16 pgm_dma_swap = 0;
ASSERT((len%8) == 0); /* length must be multiple of 8,16bit word or 4,32bit word */
/* start of critical code section*/
EMU_unit_maskit_prev = EMU_unit_maskit;
MMDSP_EMU_MASKIT(INTERRUPT_DISABLE);
/* Check that transfer is completed */
#ifdef T1XHV_SIA
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_W) != 0);
#else
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_W) != 0);
#endif
switch (swap_cfg)
{
case MTF_NO_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16);
break;
case MTF_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16_SWAP);
break;
case MTF_NO_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16);
break;
case MTF_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16_SWAP);
break;
default :
ASSERT(0);
break;
/* other not possible */
}
#ifdef T1XHV_SIA
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_W)|(pgm_dma_swap ? MTF_W : 0));
#else
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_W)|(pgm_dma_swap ? MTF_W : 0));
#endif
/* program DMA transfer */
DMA_SET_MTF_WRITE_PARAM(addr_out,incr,(len>>2));
/* start DMA transfer */
#ifdef T1XHV_SIA
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_W);
#else
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_W);
#endif
MTF_SET_REG(MTF_W_REG_ENR,0x1);
/* write all values to MTF_W Fifo */
while (len--)
{
value = *pt_src++; /* read from MMDSP table */
*ptr_mtf_w = value; /* write to fifo */
}
/*MTF_SET_REG(MTF_W_REG_DIR,0x1);*/
/*DMA_SET_REG(DMA_DIR,MTF_W);*/ /* removed according to latest HW spec */
/* end of critical code section */
/**
* if we were in a critical code section before this function, we
* remain critical
*/
MMDSP_EMU_MASKIT(EMU_unit_maskit_prev);
}
static void hwInit(void)
{
/* unmask all Interrupts */
MMDSP_EMU_MASKIT(INTERRUPT_ENABLE);
/* Enable clock for all HW blocks */
#ifndef CLOCK_GATING_POWER_MGMT
CKG_ENABLE_CLOCK(ALL_BLOCKS,ALL_BLOCKS);
#else
CKG_ENABLE_CLOCKS_RM();
#endif
#ifdef __ndk8500_a0__
DMA_SET_REG(DMA_BSM_L,(MECC_R|CD_W|CD_R|REC_W));
DMA_SET_REG(DMA_BSM_H,(IME_CWL_R|IME_TPL_R|IME_SWL_R|IME_MVF_R|IME_MVF_W|IME_CCM_W|IPA_R|RECF_W|RECF_R));
#else
DMA_SET_REG(DMA_BSM,(MECC_R|CD_W|CD_R|REC_W));
#endif
/* CONFIGURE DMA priorities */
#ifdef __ndk8500_a0__
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL0,(21<<3)); /* CUP_CTX_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL1,(13<<3)); /* MTF_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL2,(16<<3)); /* SWF_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL3,(14<<3)); /* CD_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL4,(4<<3)); /* VPP_L_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL5,(6<<3)); /* VPP_C_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL6,(17<<3)); /* VPP_PARAM_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL7,(25<<3)); /* IMC_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL8,(24<<3)); /* IME_CWL_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL9,(10<<3)); /* IME_TPL_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL10,(9<<3)); /* IME_SWL_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL11,(23<<3)); /* IME_MVF_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL12,(8<<3)); /* IPA_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL13,(1<<3)); /* RECF_R */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL14,(11<<3)); /* IME_CCM_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL15,(12<<3)); /* MTF_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL16,(2<<3)); /* SWF_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL17,(19<<3)); /* CD_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL18,(3<<3)); /* VPP_L_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL19,(5<<3)); /* VPP_C_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL20,(7<<3)); /* REC_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL21,(20<<3)); /* CUP_CTX_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL22,(18<<3)); /* CUP_DBX_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL23,(22<<3)); /* IME_MVF_W */
DMA_SET_REG_WAIT(DMA_PRIO_LEVEL24,(15<<3)); /* RECF_W */
/* from HW overview document, recommended values */
HW_MUX3TO1_WAIT(NOD_INIT1_PRIORITY) = 0x3;
HW_MUX3TO1_WAIT(NOD_INIT2_PRIORITY) = 0x1;
HW_MUX3TO1_WAIT(NOD_INIT3_PRIORITY) = 0x2;
#endif
#ifdef __ndk8500_ed__
/* updated based on 8820 cut B STBus arbitration spec 1.0 - March 2008 */
DMA_SET_REG_WAIT(DMA_PRIO_1,7<<3); /* MTF_R */
DMA_SET_REG_WAIT(DMA_PRIO_2,10<<3); /* SWF_R */
DMA_SET_REG_WAIT(DMA_PRIO_3,13<<3); /* CD_R */
DMA_SET_REG_WAIT(DMA_PRIO_4,8<<3); /* DEB_L_R */
DMA_SET_REG_WAIT(DMA_PRIO_5,8<<3); /* DEB_C_R */
DMA_SET_REG_WAIT(DMA_PRIO_6,9<<3); /* PARAM_R */
DMA_SET_REG_WAIT(DMA_PRIO_7,11<<3); /* MECC_R */
DMA_SET_REG_WAIT(DMA_PRIO_7A,11<<3); /* CUP_CTX_R */
DMA_SET_REG_WAIT(DMA_PRIO_8,7<<3); /* MTF_W */
DMA_SET_REG_WAIT(DMA_PRIO_9,10<<3); /* SWF_W */
DMA_SET_REG_WAIT(DMA_PRIO_10,13<<3); /* CD_W */
DMA_SET_REG_WAIT(DMA_PRIO_11,8<<3); /* DEB_L_W */
DMA_SET_REG_WAIT(DMA_PRIO_12,8<<3); /* DEB_C_W */
DMA_SET_REG_WAIT(DMA_PRIO_13,12<<3); /* REC_W */
DMA_SET_REG_WAIT(DMA_PRIO_14,12<<3); /* CUP_CTX_W */
DMA_SET_REG_WAIT(DMA_PRIO_15,12<<3); /* CUP_DBX_W */
#endif
#ifdef __ndk20__
DMA_SET_REG_WAIT(DMA_PRIO_1,7); /* MTF_R */
DMA_SET_REG_WAIT(DMA_PRIO_2,10); /* SWF_R */
DMA_SET_REG_WAIT(DMA_PRIO_3,13); /* CD_R */
DMA_SET_REG_WAIT(DMA_PRIO_4,8); /* DEB_L_R */
DMA_SET_REG_WAIT(DMA_PRIO_5,8); /* DEB_C_R */
DMA_SET_REG_WAIT(DMA_PRIO_6,9); /* PARAM_R */
DMA_SET_REG_WAIT(DMA_PRIO_7,14); /* MECC_R */
DMA_SET_REG_WAIT(DMA_PRIO_8,7); /* MTF_W */
DMA_SET_REG_WAIT(DMA_PRIO_9,10); /* SWF_W */
DMA_SET_REG_WAIT(DMA_PRIO_10,13); /* CD_W */
DMA_SET_REG_WAIT(DMA_PRIO_11,8); /* DEB_L_W */
DMA_SET_REG_WAIT(DMA_PRIO_12,8); /* DEB_C_W */
DMA_SET_REG_WAIT(DMA_PRIO_13,12); /* REC_W */
#endif
STPLUG_PGM();
} /* End of hwInit() function. */
