EFI_STATUS EFIAPI SetPeiCacheMode ( IN CONST EFI_PEI_SERVICES **PeiServices ) { EFI_STATUS Status; PEI_CACHE_PPI *CachePpi; EFI_BOOT_MODE BootMode; UINT64 MemoryLength; UINT64 MemOverflow; UINT64 MemoryLengthUc; UINT64 MaxMemoryLength; UINT64 LowMemoryLength; UINT64 HighMemoryLength; UINT8 Index; MTRR_SETTINGS MtrrSetting; UINT64 ValidMtrrAddressMask; // // Load Cache PPI // Status = (**PeiServices).LocatePpi ( PeiServices, &gPeiCachePpiGuid, // GUID 0, // Instance NULL, // EFI_PEI_PPI_DESCRIPTOR (void **)&CachePpi // PPI ); if (!EFI_ERROR(Status)) { // // Clear the CAR Settings (Default Cache Type => UC) // DEBUG ((EFI_D_INFO, "Reset cache attribute and disable CAR. \n")); CachePpi->ResetCache( (EFI_PEI_SERVICES**)PeiServices, CachePpi ); } // // Variable initialization // LowMemoryLength = 0; HighMemoryLength = 0; MemoryLengthUc = 0; Status = (*PeiServices)->GetBootMode ( PeiServices, &BootMode ); ValidMtrrAddressMask = InitializeAddressMtrrMask (); // // Determine memory usage // GetMemorySize ( PeiServices, &LowMemoryLength, &HighMemoryLength ); LowMemoryLength = (EFI_PHYSICAL_ADDRESS)MmPci32( 0, 0, 2, 0, 0x70); LowMemoryLength &= 0xFFF00000ULL; MaxMemoryLength = LowMemoryLength; // // Round up to nearest 256MB with high memory and 64MB w/o high memory // if (HighMemoryLength != 0 ) { MemOverflow = (LowMemoryLength & 0x0fffffff); if (MemOverflow != 0) { MaxMemoryLength = LowMemoryLength + (0x10000000 - MemOverflow); } } else { MemOverflow = (LowMemoryLength & 0x03ffffff); if (MemOverflow != 0) { MaxMemoryLength = LowMemoryLength + (0x4000000 - MemOverflow); } } ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS)); for (Index = 0; Index < 2; Index++) { MtrrSetting.Fixed.Mtrr[Index]=0x0606060606060606; } for (Index = 2; Index < 11; Index++) { MtrrSetting.Fixed.Mtrr[Index]=0x0505050505050505; } // // Cache the flash area to improve the boot performance in PEI phase // Index = 0; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Base)->Uint64 = FixedPcdGet32 (PcdFlashAreaBaseAddress); ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Base)->Bits.Type = CacheWriteProtected; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Mask)->Uint64 = (~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Mask)->Bits.V = 1; Index ++; MemOverflow =0; while (MaxMemoryLength > MemOverflow){ MemoryLength = MaxMemoryLength - MemOverflow; MemoryLength = GetPowerOfTwo64 (MemoryLength); ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = MemOverflow & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheWriteBack; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLength - 1)) & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1; MemOverflow += MemoryLength; Index++; } MemoryLength = LowMemoryLength; while (MaxMemoryLength != MemoryLength) { MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength); ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = (MaxMemoryLength - MemoryLengthUc) & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheUncacheable; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLengthUc - 1)) & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1; MaxMemoryLength -= MemoryLengthUc; Index++; } MemOverflow =0x100000000; while (HighMemoryLength > 0) { MemoryLength = HighMemoryLength; MemoryLength = GetPowerOfTwo64 (MemoryLength); if (MemoryLength > MemOverflow){ MemoryLength = MemOverflow; } ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Uint64 = MemOverflow & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Base)->Bits.Type = CacheWriteBack; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Uint64 = (~(MemoryLength - 1)) & ValidMtrrAddressMask; ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index].Mask)->Bits.V = 1; MemOverflow += MemoryLength; HighMemoryLength -= MemoryLength; Index++; } for (Index = 0; Index < MTRR_NUMBER_OF_VARIABLE_MTRR; Index++) { if (MtrrSetting.Variables.Mtrr[Index].Base == 0){ break; } DEBUG ((EFI_D_INFO, "Base=%lx, Mask=%lx\n",MtrrSetting.Variables.Mtrr[Index].Base ,MtrrSetting.Variables.Mtrr[Index].Mask)); } // // set FE/E bits for IA32_MTRR_DEF_TYPE // MtrrSetting.MtrrDefType |= 3 <<10; MtrrSetAllMtrrs(&MtrrSetting); // // Dump MTRR Setting // MtrrDebugPrintAllMtrrs (); return EFI_SUCCESS; }
/** Install Firmware Volume Hob's once there is main memory @param[in] PeiServices General purpose services available to every PEIM. @param[in] NotifyDescriptor Notify that this module published. @param[in] Ppi PPI that was installed. @retval EFI_SUCCESS The function completed successfully. **/ EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback ( IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi ) { EFI_CPUID_REGISTER FeatureInfo; UINT8 CpuAddressWidth; UINT32 RootComplexBar; UINT32 PmcBase; UINT32 IoBase; UINT32 IlbBase; UINT32 SpiBase; UINT32 MphyBase; UINT32 PunitBase; // // Pulish memory type info // PublishMemoryTypeInfo (); RootComplexBar = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA) & B_PCH_LPC_RCBA_BAR; DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar)); ASSERT (RootComplexBar != 0 && RootComplexBar != B_PCH_LPC_RCBA_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), RootComplexBar, 0x1000 ); PmcBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR; DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase)); ASSERT (PmcBase != 0 && PmcBase != B_PCH_LPC_PMC_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), PmcBase, 0x1000 ); IoBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR; DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase)); ASSERT (IoBase != 0 && IoBase != B_PCH_LPC_IO_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IoBase, 0x40000 ); IlbBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE) & B_PCH_LPC_ILB_BASE_BAR; DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase)); ASSERT (IlbBase != 0 && IlbBase != B_PCH_LPC_ILB_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IlbBase, 0x2000 ); SpiBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR; DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase)); ASSERT (SpiBase != 0 && SpiBase != B_PCH_LPC_SPI_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), SpiBase, 0x1000 ); MphyBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE) & B_PCH_LPC_MPHY_BASE_BAR; DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase)); ASSERT (MphyBase != 0 && MphyBase != B_PCH_LPC_MPHY_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), MphyBase, 0x100000 ); PunitBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PUNIT_BASE) & B_PCH_LPC_PUNIT_BASE_BAR; DEBUG ((EFI_D_INFO, "PunitBase : 0x%x\n", PunitBase)); ASSERT (PunitBase != 0 && PunitBase != B_PCH_LPC_PUNIT_BASE_BAR); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), PunitBase, 0x1000 ); // // Local APIC // DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS)); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), LOCAL_APIC_ADDRESS, 0x1000 ); // // IO APIC // DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS)); BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IO_APIC_ADDRESS, 0x1000 ); // // Adding the PCIE Express area to the E820 memory table as type 2 memory. // BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), ((UINTN)PcdGet64(PcdPciExpressBaseAddress)), //PlatformInfo->PciData.PciExpressBase, 0x10000000 //PlatformInfo->PciData.PciExpressSize ); // // Adding the Flashpart to the E820 memory table as type 2 memory. // DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", PcdGet32(PcdFlashAreaBaseAddress))); BuildResourceDescriptorHob ( EFI_RESOURCE_FIRMWARE_DEVICE, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), PcdGet32(PcdFlashAreaBaseAddress), PcdGet32(PcdFlashAreaSize) ); // // Create a CPU hand-off information // CpuAddressWidth = 32; AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) { AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF); } BuildCpuHob(CpuAddressWidth, 16); return EFI_SUCCESS; }
EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback ( IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi ) { EFI_STATUS Status; EFI_BOOT_MODE BootMode; EFI_CPUID_REGISTER FeatureInfo; UINT8 CpuAddressWidth; UINT16 Pm1Cnt; EFI_PEI_HOB_POINTERS Hob; EFI_PLATFORM_INFO_HOB *PlatformInfo; UINT32 RootComplexBar; UINT32 PmcBase; UINT32 IoBase; UINT32 IlbBase; UINT32 SpiBase; UINT32 MphyBase; // // Get Platform Info HOB // Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); ASSERT (Hob.Raw != NULL); PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw); Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); // // Check if user wants to turn off in PEI phase // if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) { CheckPowerOffNow(); } else { Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT); Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP; IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt); } #ifndef MINNOW2_FSP_BUILD // // Set PEI cache mode here // SetPeiCacheMode (PeiServices); #endif // // Pulish memory tyoe info // PublishMemoryTypeInfo (); // // Work done if on a S3 resume // if (BootMode == BOOT_ON_S3_RESUME) { // //Program the side band packet register to send a sideband message to Punit //To indicate that DRAM has been initialized and PUNIT FW base address in memory. // return EFI_SUCCESS; } RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), RootComplexBar, 0x1000 ); DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar)); PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), PmcBase, 0x1000 ); DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase)); IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IoBase, 0x4000 ); DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase)); IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IlbBase, 0x1000 ); DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase)); SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), SpiBase, 0x1000 ); DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase)); MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR; BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), MphyBase, 0x100000 ); DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase)); // // Local APIC // BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), LOCAL_APIC_ADDRESS, 0x1000 ); DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS)); // // IO APIC // BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), IO_APIC_ADDRESS, 0x1000 ); DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS)); // // Adding the PCIE Express area to the E820 memory table as type 2 memory. // BuildResourceDescriptorHob ( EFI_RESOURCE_MEMORY_MAPPED_IO, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), PlatformInfo->PciData.PciExpressBase, PlatformInfo->PciData.PciExpressSize ); DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase)); // // Adding the Flashpart to the E820 memory table as type 2 memory. // BuildResourceDescriptorHob ( EFI_RESOURCE_FIRMWARE_DEVICE, (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), FixedPcdGet32 (PcdFlashAreaBaseAddress), FixedPcdGet32 (PcdFlashAreaSize) ); DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress))); // // Create a CPU hand-off information // CpuAddressWidth = 32; AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) { AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF); } BuildCpuHob(CpuAddressWidth, 16); ASSERT_EFI_ERROR (Status); return Status; }