void CPU_Reset()
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
SCB->AIRCR = (0x5FA << SCB_AIRCR_VECTKEY_Pos) // unlock key
| (1 << SCB_AIRCR_SYSRESETREQ_Pos); // reset request
while(1); // wait for reset
}
void CPU_Sleep( SLEEP_LEVEL level, UINT64 wakeEvents )
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
switch(level) {
case SLEEP_LEVEL__DEEP_SLEEP: // stop
SCB->SCR |= SCB_SCR_SLEEPDEEP;
PWR->CR |= PWR_CR_CWUF | PWR_CR_LPDS; // low power deepsleep
__WFI(); // stop clocks and wait for external interrupt
RCC->CR |= RCC_CR_PLLON | RCC_CR_HSEON; // HSE & PLL on
SCB->SCR &= ~SCB_SCR_SLEEPDEEP; // reset deepsleep
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR |= RCC_CFGR_SW_PLL; // sysclk = pll out
RCC->CR &= ~RCC_CR_HSION; // HSI off
return;
case SLEEP_LEVEL__OFF: // standby
SCB->SCR |= SCB_SCR_SLEEPDEEP;
PWR->CR |= PWR_CR_CWUF | PWR_CR_PDDS; // power down deepsleep
__WFI(); // soft power off, never returns
return;
default: // sleep
PWR->CR |= PWR_CR_CWUF;
__WFI(); // sleep and wait for interrupt
return;
}
}
void CPU_Sleep( SLEEP_LEVEL level, UINT64 wakeEvents )
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
PWR->CR &= ~(PWR_CR_LPDS | PWR_CR_PDDS); // reset deepsleep bits
switch(level)
{
case SLEEP_LEVEL__DEEP_SLEEP: // stop
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= PWR_CR_CWUF | PWR_CR_LPDS; // low power deepsleep
break;
case SLEEP_LEVEL__OFF: // standby
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= PWR_CR_CWUF | PWR_CR_PDDS; // power down deepsleep
break;
default: // sleep
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; // no deepsleep
PWR->CR |= PWR_CR_CWUF;
break;
}
__WFI(); // sleep and wait for interrupt
}
void HAL_CPU_Sleep( SLEEP_LEVEL level, UINT64 wakeEvents )
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
switch(level) {
case SLEEP_LEVEL__DEEP_SLEEP: // stop
// stop peripherals if needed
if (g_STM32F4_stopHandler != NULL)
g_STM32F4_stopHandler();
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= PWR_CR_CWUF | PWR_CR_FPDS | PWR_CR_LPDS; // low power deepsleep
__WFI(); // stop clocks and wait for external interrupt
#if SYSTEM_CRYSTAL_CLOCK_HZ != 0
RCC->CR |= RCC_CR_HSEON; // HSE on
#endif
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; // reset deepsleep
while(!(RCC->CR & RCC_CR_HSERDY));
RCC->CR |= RCC_CR_PLLON; // pll on
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR |= RCC_CFGR_SW_PLL; // sysclk = pll out
#if SYSTEM_CRYSTAL_CLOCK_HZ != 0
RCC->CR &= ~RCC_CR_HSION; // HSI off
#endif
// restart peripherals if needed
if (g_STM32F4_restartHandler != NULL)
g_STM32F4_restartHandler();
return;
case SLEEP_LEVEL__OFF: // standby
// stop peripherals if needed
if (g_STM32F4_stopHandler != NULL)
g_STM32F4_stopHandler();
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= PWR_CR_CWUF | PWR_CR_PDDS; // power down deepsleep
__WFI(); // soft power off, never returns
return;
default: // sleep
PWR->CR |= PWR_CR_CWUF;
__WFI(); // sleep and wait for interrupt
return;
}
}
BOOL CPU_IsSoftRebootSupported ()
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
return TRUE;
}
void CPU_Halt() // unrecoverable error
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
while(1);
}
BOOL CPU_Initialize()
{
NATIVE_PROFILE_HAL_PROCESSOR_POWER();
CPU_INTC_Initialize();
return TRUE;
}
