static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); SystemInit(); #ifdef CONFIG_NRF_ENABLE_ICACHE /* Enable the instruction cache */ NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk; #endif #if defined(CONFIG_SOC_DCDC_NRF52X) nrf_power_dcdcen_set(true); #endif _ClearFaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
/** * @brief Perform basic hardware initialization * * Initialize the interrupt controller device drivers. * Also initialize the timer device driver, if required. * * @return 0 */ static int silabs_efm32wg_init(struct device *arg) { ARG_UNUSED(arg); int oldLevel; /* old interrupt lock level */ /* disable interrupts */ oldLevel = irq_lock(); /* handle chip errata */ CHIP_Init(); _ClearFaults(); /* Initialize system clock according to CONFIG_CMU settings */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; }
static int ti_cc2650(struct device *dev) { ARG_UNUSED(dev); NMI_INIT(); setup_modules_prcm(); return 0; }
static int ti_lm3s6965_init(struct device *arg) { ARG_UNUSED(arg); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int atmel_sam3_init(struct device *arg) { uint32_t key; ARG_UNUSED(arg); /* Note: * Magic numbers below are obtained by reading the registers * when the SoC was running the SAM-BA bootloader * (with reserved bits set to 0). */ key = irq_lock(); /* Setup the vector table offset register (VTOR), * which is located at the beginning of flash area. */ _scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS); /* Setup the flash controller. * The bootloader is running @ 48 MHz with * FWS == 2. * When running at 84 MHz, FWS == 4 seems * to be more stable, and allows the board * to boot. */ __EEFC0->fmr = 0x00000400; __EEFC1->fmr = 0x00000400; /* Clear all faults */ _ScbMemFaultAllFaultsReset(); _ScbBusFaultAllFaultsReset(); _ScbUsageFaultAllFaultsReset(); _ScbHardFaultAllFaultsReset(); /* Setup master clock */ clock_init(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
static int nordicsemi_nrf51_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); /* Note: * Magic numbers below are obtained by reading the registers * when the SoC was running the SAM-BA bootloader * (with reserved bits set to 0). */ key = irq_lock(); /* Prepare the peripherals for use as indicated by the PAN 26 "System: * Manual setup is required to enable the use of peripherals" found at * Product Anomaly document for your device found at * https://www.nordicsemi.com/. The side effect of executing these * instructions in the devices that do not need it is that the new * peripherals in the second generation devices (LPCOMP for example) * will not be available. */ if (ftpan_26()) { *(volatile u32_t *)0x40000504 = 0xC007FFDF; *(volatile u32_t *)0x40006C18 = 0x00008000; } /* Disable PROTENSET registers under debug, as indicated by PAN 59 * "MPU: Reset value of DISABLEINDEBUG register is incorrect" found * at Product Anomaly document for your device found at * https://www.nordicsemi.com/. */ if (ftpan_59()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; } /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
static int fsl_frdm_k64f_init(struct device *arg) { ARG_UNUSED(arg); int oldLevel; /* old interrupt lock level */ #if !defined(CONFIG_HAS_SYSMPU) u32_t temp_reg; #endif /* !CONFIG_HAS_SYSMPU */ /* disable interrupts */ oldLevel = irq_lock(); /* release I/O power hold to allow normal run state */ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; #if !defined(CONFIG_HAS_SYSMPU) /* * Disable memory protection and clear slave port errors. * Note that the K64F does not implement the optional ARMv7-M memory * protection unit (MPU), specified by the architecture (PMSAv7), in the * Cortex-M4 core. Instead, the processor includes its own MPU module. */ temp_reg = SYSMPU->CESR; temp_reg &= ~SYSMPU_CESR_VLD_MASK; temp_reg |= SYSMPU_CESR_SPERR_MASK; SYSMPU->CESR = temp_reg; #endif /* !CONFIG_HAS_SYSMPU */ _ClearFaults(); /* Initialize PLL/system clock to 120 MHz */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * Assumption: * MAINCLK = 24Mhz * * @return 0 */ static int arm_beetle_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); /* Setup various clocks and wakeup sources */ soc_power_init(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int atmel_sam3x_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); /* Note: * Magic numbers below are obtained by reading the registers * when the SoC was running the SAM-BA bootloader * (with reserved bits set to 0). */ key = irq_lock(); /* Setup the flash controller. * The bootloader is running @ 48 MHz with * FWS == 2. * When running at 84 MHz, FWS == 4 seems * to be more stable, and allows the board * to boot. */ __EEFC0->fmr = 0x00000400; __EEFC1->fmr = 0x00000400; _ClearFaults(); /* Setup master clock */ clock_init(); /* Disable watchdog timer, not used by system */ __WDT->mr |= WDT_DISABLE; /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int stm32f1_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); _ClearFaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 8 MHz from HSI */ SystemCoreClock = 8000000; return 0; }
static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); #ifdef CONFIG_SOC_NRF52832 nordicsemi_nrf52832_init(); #endif #ifdef CONFIG_SOC_NRF52840 nordicsemi_nrf52840_init(); #endif /* Enable the FPU if the compiler used floating point unit * instructions. Since the FPU consumes energy, remember to * disable FPU use in the compiler if floating point unit * operations are not used in your code. */ #if defined(CONFIG_FLOAT) SCB->CPACR |= (3UL << 20) | (3UL << 22); __DSB(); __ISB(); #endif /* Configure NFCT pins as GPIOs if NFCT is not to be used in * your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, * two GPIOs (see Product Specification to see which ones) * will be reserved for NFC and will not be available as * normal GPIOs. */ #if defined(CONFIG_NFCT_PINS_AS_GPIOS) if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NVIC_SystemReset(); } #endif _ClearFaults(); /* Setup master clock */ clock_init(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
static ALWAYS_INLINE void clkInit(void) { /* * Core clock: 48MHz * Bus clock: 24MHz */ const mcg_pll_config_t pll0Config = { .enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0, }; const sim_clock_config_t simConfig = { .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ .er32kSrc = 3U, /* ERCLK32K selection, use LPO. */ .clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */ }; const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ, .capLoad = 0, #if defined(CONFIG_OSC_EXTERNAL) .workMode = kOSC_ModeExt, #elif defined(CONFIG_OSC_LOW_POWER) .workMode = kOSC_ModeOscLowPower, #elif defined(CONFIG_OSC_HIGH_GAIN) .workMode = kOSC_ModeOscHighGain, #else #error "An oscillator mode must be defined" #endif .oscerConfig = { .enableMode = kOSC_ErClkEnable, #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \ FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) .erclkDiv = 0U, #endif } }; CLOCK_SetSimSafeDivs(); CLOCK_InitOsc0(&oscConfig); /* Passing the XTAL0 frequency to clock driver. */ CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ); CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config); CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0); CLOCK_SetSimConfig(&simConfig); #ifdef CONFIG_UART_MCUX_LPSCI_0 CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK); #endif } static int kl2x_init(struct device *arg) { ARG_UNUSED(arg); int oldLevel; /* old interrupt lock level */ /* disable interrupts */ oldLevel = irq_lock(); /* Disable the watchdog */ SIM->COPC = 0; /* Initialize system clock to 48 MHz */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; } SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
static int fsl_frdm_k64f_init(struct device *arg) { ARG_UNUSED(arg); /* System Integration module */ volatile struct K20_SIM *sim_p = (volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM; /* Power Mgt Control module */ volatile struct K6x_PMC *pmc_p = (volatile struct K6x_PMC *)PERIPH_ADDR_BASE_PMC; /* Power Mgt Control module */ volatile struct K6x_MPU *mpu_p = (volatile struct K6x_MPU *)PERIPH_ADDR_BASE_MPU; int oldLevel; /* old interrupt lock level */ uint32_t temp_reg; /* disable interrupts */ oldLevel = irq_lock(); /* enable the port clocks */ sim_p->scgc5.value |= (SIM_SCGC5_PORTA_CLK_EN | SIM_SCGC5_PORTB_CLK_EN | SIM_SCGC5_PORTC_CLK_EN | SIM_SCGC5_PORTD_CLK_EN | SIM_SCGC5_PORTE_CLK_EN); /* release I/O power hold to allow normal run state */ pmc_p->regsc.value |= PMC_REGSC_ACKISO_MASK; /* * Disable memory protection and clear slave port errors. * Note that the K64F does not implement the optional ARMv7-M memory * protection unit (MPU), specified by the architecture (PMSAv7), in the * Cortex-M4 core. Instead, the processor includes its own MPU module. */ temp_reg = mpu_p->ctrlErrStatus.value; temp_reg &= ~MPU_VALID_MASK; temp_reg |= MPU_SLV_PORT_ERR_MASK; mpu_p->ctrlErrStatus.value = temp_reg; /* clear all faults */ _ScbMemFaultAllFaultsReset(); _ScbBusFaultAllFaultsReset(); _ScbUsageFaultAllFaultsReset(); _ScbHardFaultAllFaultsReset(); /* * Initialize the clock dividers for: * core and system clocks = 120 MHz (PLL/OUTDIV1) * bus clock = 60 MHz (PLL/OUTDIV2) * FlexBus clock = 40 MHz (PLL/OUTDIV3) * Flash clock = 24 MHz (PLL/OUTDIV4) */ sim_p->clkdiv1.value = ( (SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) << SIM_CLKDIV1_OUTDIV1_SHIFT) | (SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) << SIM_CLKDIV1_OUTDIV2_SHIFT) | (SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) << SIM_CLKDIV1_OUTDIV3_SHIFT) | (SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) << SIM_CLKDIV1_OUTDIV4_SHIFT)); /* Initialize PLL/system clock to 120 MHz */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; }