/**
* \brief Initializes the USARTDma structure and the corresponding USART & DMA .
* hardware select value.
* The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
* The DMA channels are freed automatically when no USART command processing.
*
* \param pUSARTD Pointer to a UsartDma instance.
* \param pUsartHw Associated USART peripheral.
* \param usartId USART peripheral identifier.
* \param UsartClk USART clock.
* \param pXdmad Pointer to a Dmad instance.
*/
uint32_t USARTD_Configure(UsartDma *pUsartd ,
uint8_t usartId,
uint32_t UsartMode,
uint32_t BaudRate,
uint32_t UsartClk)
{
/* Enable the peripheral clock in the PMC*/
PMC_EnablePeripheral(usartId);
/* Initialize the USART structure */
pUsartd->usartId = usartId;
if (usartId == ID_USART0)
pUsartd->pUsartHw = USART0;
if (usartId == ID_USART1)
pUsartd->pUsartHw = USART1;
if (usartId == ID_USART2)
pUsartd->pUsartHw = USART2;
/* Enable the USART Peripheral ,Execute a software reset of the USART,
Configure USART in Master Mode*/
USART_Configure (pUsartd->pUsartHw, UsartMode, BaudRate, UsartClk);
/* Check if DMA IRQ is enable; if not clear pending IRQs in init it */
if (!(NVIC_GetActive(XDMAC_IRQn)))
NVIC_ClearPendingIRQ(XDMAC_IRQn);
return 0;
}
int vIRQ_GetLevel(void)
{
/* if uVisor is disabled we use the standard priority levels */
if (__uvisor_mode == 0) {
/* check if an IRQn is active (an ISR is being served) */
uint32_t ipsr = __get_IPSR();
int irqn = (int) (ipsr & 0x1FF) - NVIC_USER_IRQ_OFFSET;
if (irqn >= NVIC_NUM_VECTORS || !ipsr || !NVIC_GetActive((IRQn_Type) irqn)) {
return -1;
}
/* return the priority level of the active IRQ */
/* if we are in a system interrupt we do not provide the actual
* priority level, which is usually negative, since we already use -1
* for stating "no IRQn is active". This is consistent with the
* behavior of the actual uVisor-managed API, as this call will never
* come from a system interrupt. The caller can still use this
* information to assess that an IRQn is actually active (0 = lowest
* priority) */
if (irqn < 0) {
return 0;
}
else {
return NVIC_GetPriority((IRQn_Type) irqn);
}
}
else {
return UVISOR_SVC(UVISOR_SVC_ID_IRQ_LEVEL_GET, "");
}
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
/* If the EXTI0 IRQ Handler was preempted by SysTick Handler */
if(NVIC_GetActive(EXTI0_IRQn) != (IRQn_Type) RESET)
{
PreemptionOccured = TRUE;
}
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
/* If the EXTI8 IRQ Handler was preempted by SysTick Handler */
if(NVIC_GetActive(SEL_BUTTON_EXTI_IRQn) != 0)
{
PreemptionOccured = 1;
}
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
/* If the WAKEUP_BUTTON_EXTI IRQ Handler (EXTI0_IRQHandler) was preempted
by SysTick Handler */
if(NVIC_GetActive(WAKEUP_BUTTON_EXTI_IRQn) != 0)
{
PreemptionOccured = 1;
}
}
/**
* \brief This function initialize the appropriate DMA channel for Rx/Tx channel of SPI or SMC
* \returns 0 if the transfer has been started successfully; otherwise returns
* ILI9488_ERROR_XX is the driver is in use, or ILI9488_ERROR_XX if the command is not
* valid.
*/
static uint8_t _ILI9488DmaConfigChannels(void)
{
uint32_t srcType,dstType;
/* Driver initialize */
XDMAD_Initialize( ili9488Dma.xdmaD, 0 );
XDMAD_FreeChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel);
XDMAD_FreeChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel);
#if !defined(BOARD_LCD_SMC)
srcType = XDMAD_TRANSFER_MEMORY;
dstType = ili9488Dma.spiId;
#else
srcType = XDMAD_TRANSFER_MEMORY;
dstType = XDMAD_TRANSFER_MEMORY;
#endif
/* Allocate a DMA channel for ILI9488_SPI TX. */
ili9488Dma.ili9488DmaTxChannel = XDMAD_AllocateChannel( ili9488Dma.xdmaD, srcType, dstType);
{
if ( ili9488Dma.ili9488DmaTxChannel == XDMAD_ALLOC_FAILED )
{
return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL;
}
}
/* Allocate a DMA channel for ILI9488_SPI RX. */
ili9488Dma.ili9488DmaRxChannel = XDMAD_AllocateChannel( ili9488Dma.xdmaD, dstType, srcType);
{
if ( ili9488Dma.ili9488DmaRxChannel == XDMAD_ALLOC_FAILED )
{
return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL;
}
}
/* Setup callbacks for ILI9488_SPI RX */
XDMAD_SetCallback(ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel, (XdmadTransferCallback)_ILI9488_Rx_CB, &ili9488Dma);
if (XDMAD_PrepareChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel ))
return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL;
/* Setup callbacks for ILI9488_SPI TX (ignored) */
XDMAD_SetCallback(ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel, (XdmadTransferCallback)_ILI9488_Tx_CB, &ili9488Dma);
if ( XDMAD_PrepareChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel ))
return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL;
/* Check if DMA IRQ is enable; if not Enable it */
if(!(NVIC_GetActive(XDMAC_IRQn)))
{
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
}
return 0;
}
/**
* \brief This function initialize the appropriate DMA channel for Rx channel
* of USART
* \param pUsartd Pointer to a UsartDma instance.
* \param pRxCh Pointer to TxChannel configuration
* \returns 0 if the transfer has been started successfully;
* otherwise returns USARTD_ERROR_LOCK is the driver is in use, or
* USARTD_ERROR if the command is not valid.
*/
uint32_t USARTD_EnableRxChannels(UsartDma *pUsartd, UsartChannel *pRxCh)
{
uint32_t Channel;
assert(pRxCh);
/* Init USART Rx Channel. */
pUsartd->pRxChannel = pRxCh;
/* Enables the USART to receive data. */
USART_SetReceiverEnabled (pUsartd->pUsartHw , ENABLE);
/* Allocate a DMA channel for USART0/1 RX. */
Channel = XDMAD_AllocateChannel(pUsartd->pXdmad, pUsartd->usartId,
XDMAD_TRANSFER_MEMORY);
if (Channel == XDMAD_ALLOC_FAILED)
return USARTD_ERROR;
pRxCh->ChNum = Channel;
/* Setup callbacks for USART RX */
if (pUsartd->pRxChannel->callback) {
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum,
(XdmadTransferCallback)pRxCh->callback, pRxCh->pArgument);
} else {
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum,
(XdmadTransferCallback)USARTD_Rx_Cb, pUsartd);
}
if (XDMAD_PrepareChannel(pUsartd->pXdmad, pRxCh->ChNum))
return USARTD_ERROR;
if (_configureRxDma(pUsartd , pUsartd->pRxChannel))
return USARTD_ERROR_LOCK;
/* Check if DMA IRQ is enable; if not Enable it */
if (!(NVIC_GetActive(XDMAC_IRQn))) {
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
}
return 0;
}
/**
* \brief This function initialize the appropriate DMA channel for Tx channel of UART
*
* \param pUartd Pointer to a UartDma instance.
* \param pTxCh Pointer to RxChannel configuration
* \returns 0 if the transfer has been started successfully; otherwise returns
* UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR if the command is not
* valid.
*/
uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh)
{
Uart *pUartHw = pUartd->pUartHw;
uint32_t Channel;
/* Init USART Tx Channel. */
pUartd->pTxChannel = pTxCh;
/* Allocate a DMA channel for UART TX. */
Channel = XDMAD_AllocateChannel( pUartd->pXdmad, XDMAD_TRANSFER_MEMORY, pUartd->uartId);
if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED )
{
return USARTD_ERROR;
}
pTxCh->ChNum = Channel ;
/* Setup callbacks for UART TX */
if(pUartd->pTxChannel->callback)
{
XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)pTxCh->callback, pTxCh->pArgument);
}
else
{
XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)UARTD_Tx_Cb, pUartd);
}
if ( XDMAD_PrepareChannel( pUartd->pXdmad, pTxCh->ChNum ))
return USARTD_ERROR;
if (_configureUartTxDma(pUartHw, pUartd->pXdmad, pTxCh))
return USARTD_ERROR_LOCK;
/* Check if DMA IRQ is enable; if not Enable it */
if(!(NVIC_GetActive(XDMAC_IRQn)))
{
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
}
return 0;
}
/**
* \brief Initializes the UartDma structure and the corresponding UART & DMA .
* hardware select value.
* The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
* The DMA channels are freed automatically when no UART command processing.
*
* \param pUartd Pointer to a UartDma instance.
* \param pUartHw Associated UART peripheral.
* \param uartId UART peripheral identifier.
* \param uartMode UART peripheral identifier.*
* \param baud UART baud rate
* \param clk UART ref clock
* \param pXdmad Pointer to a Dmad instance.
*/
uint32_t UARTD_Configure( UartDma *pUartd ,
uint8_t uartId,
uint32_t uartMode,
uint32_t baud,
uint32_t clk)
{
/* Enable the peripheral clock in the PMC*/
PMC_EnablePeripheral( uartId );
/* Initialize the UART structure */
pUartd->uartId = uartId;
if (uartId == ID_UART0)
pUartd->pUartHw = UART0;
if (uartId == ID_UART1)
pUartd->pUartHw = UART1;
if (uartId == ID_UART2)
pUartd->pUartHw = UART2;
if (uartId == ID_UART3)
pUartd->pUartHw = UART3;
if (uartId == ID_UART4)
pUartd->pUartHw = UART4;
pUartd->pXdmad->pXdmacs = XDMAC;
/* Enable the UART Peripheral ,Execute a software reset of the UART,
Configure UART in Master Mode*/
UART_Configure ( pUartd->pUartHw, uartMode, baud, clk);
/* Driver initialize */
XDMAD_Initialize( pUartd->pXdmad, 0 );
/* Check if DMA IRQ is enable; if not clear pending IRQs in init it */
if(!(NVIC_GetActive(XDMAC_IRQn))) {
NVIC_ClearPendingIRQ(XDMAC_IRQn);
}
return 0;
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
\brief Test case: TC_CoreFunc_EnDisIRQ
\details
Check expected behavior of interrupt related control functions:
- __disable_irq() and __enable_irq()
- NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ
- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ
- NVIC_GetActive (not on Cortex-M0/M0+)
*/
void TC_CoreFunc_EnDisIRQ (void)
{
// Globally disable all interrupt servicing
__disable_irq();
// Enable the interrupt
NVIC_EnableIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) != 0U);
// Clear its pending state
NVIC_ClearPendingIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Register test interrupt handler.
TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
irqTaken = 0U;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
irqActive = UINT32_MAX;
#endif
// Set the interrupt pending state
NVIC_SetPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt is not taken
ASSERT_TRUE(irqTaken == 0U);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
#endif
// Globally enable interrupt servicing
__enable_irq();
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt was taken
ASSERT_TRUE(irqTaken == 1U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(irqActive != 0U);
ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
#endif
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Disable interrupt
NVIC_DisableIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) == 0U);
// Set interrupt pending
NVIC_SetPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt is not taken again
ASSERT_TRUE(irqTaken == 1U);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
// Clear interrupt pending
NVIC_ClearPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Globally disable interrupt servicing
__disable_irq();
}
static void TC_CoreFunc_EnDisIRQIRQHandler(void) {
++irqTaken;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
irqActive = NVIC_GetActive(WDT_IRQn);
#endif
}
/*__STATIC_INLINE*/ uint32_t CMSIS_STUB_NVIC_GetActive(IRQn_Type IRQn)
{
return NVIC_GetActive(IRQn);
}
MAL_DEFS_INLINE void mal_i2c_disable_interrupt(mal_i2c_s *handle, mal_i2c_interrupt_state_s *state) {
state->active = NVIC_GetActive(handle->irq);
NVIC_DisableIRQ(handle->irq);
__DSB();
__ISB();
}