//-----------------------------------------------------------------------------
static void sys_init(void)
{
// Set flash wait states to maximum for 48 MHz operation
NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS(2) | NVMCTRL_CTRLB_MANW;
// Switch to 48MHz clock (disable prescaler)
OSCCTRL->OSC48MDIV.reg = OSCCTRL_OSC48MDIV_DIV(0);
while (OSCCTRL->OSC48MSYNCBUSY.reg);
}
/**
* \brief Sets the up the NVM hardware module based on the configuration.
*
* Writes a given configuration of a NVM controller configuration to the
* hardware module, and initializes the internal device struct
*
* \param[in] config Configuration settings for the NVM controller
*
* \note The security bit must be cleared in order successfully use this
* function. This can only be done by a chip erase.
*
* \return Status of the configuration procedure.
*
* \retval STATUS_OK If the initialization was a success
* \retval STATUS_BUSY If the module was busy when the operation was attempted
* \retval STATUS_ERR_IO If the security bit has been set, preventing the
* EEPROM and/or auxiliary space configuration from being
* altered
*/
enum status_code nvm_set_config(
const struct nvm_config *const config)
{
/* Sanity check argument */
Assert(config);
/* Get a pointer to the module hardware instance */
Nvmctrl *const nvm_module = NVMCTRL;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL);
/* Clear error flags */
nvm_module->STATUS.reg |= NVMCTRL_STATUS_MASK;
/* Check if the module is busy */
if (!nvm_is_ready()) {
return STATUS_BUSY;
}
/* Writing configuration to the CTRLB register */
nvm_module->CTRLB.reg =
NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
NVMCTRL_CTRLB_RWS(config->wait_states) |
((config->disable_cache & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) |
NVMCTRL_CTRLB_READMODE(config->cache_readmode);
/* Initialize the internal device struct */
_nvm_dev.page_size = (8 << nvm_module->PARAM.bit.PSZ);
_nvm_dev.number_of_pages = nvm_module->PARAM.bit.NVMP;
_nvm_dev.manual_page_write = config->manual_page_write;
/* If the security bit is set, the auxiliary space cannot be written */
if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) {
return STATUS_ERR_IO;
}
return STATUS_OK;
}
/**
* @brief Configure clock sources and the cpu frequency
*/
static void clk_init(void)
{
/* enable clocks for the power, sysctrl and gclk modules */
PM->APBAMASK.reg = (PM_APBAMASK_PM | PM_APBAMASK_SYSCTRL |
PM_APBAMASK_GCLK);
/* adjust NVM wait states, see table 42.30 (p. 1070) in the datasheet */
#if (CLOCK_CORECLOCK > 24000000)
PM->APBAMASK.reg |= PM_AHBMASK_NVMCTRL;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
PM->APBAMASK.reg &= ~PM_AHBMASK_NVMCTRL;
#endif
/* configure internal 8MHz oscillator to run without prescaler */
SYSCTRL->OSC8M.bit.PRESC = 0;
SYSCTRL->OSC8M.bit.ONDEMAND = 1;
SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
SYSCTRL->OSC8M.bit.ENABLE = 1;
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
#if CLOCK_USE_PLL
/* reset the GCLK module so it is in a known state */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* setup generic clock 1 to feed DPLL with 1MHz */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
GCLK_GENDIV_ID(1));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_ID(1));
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(1) |
GCLK_CLKCTRL_ID(1) |
GCLK_CLKCTRL_CLKEN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* enable PLL */
SYSCTRL->DPLLRATIO.reg = (SYSCTRL_DPLLRATIO_LDR(CLOCK_PLL_MUL));
SYSCTRL->DPLLCTRLB.reg = (SYSCTRL_DPLLCTRLB_REFCLK_GCLK);
SYSCTRL->DPLLCTRLA.reg = (SYSCTRL_DPLLCTRLA_ENABLE);
while(!(SYSCTRL->DPLLSTATUS.reg &
(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK))) {}
/* select the PLL as source for clock generator 0 (CPU core clock) */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_PLL_DIV) |
GCLK_GENDIV_ID(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_FDPLL |
GCLK_GENCTRL_ID(0));
#else /* do not use PLL, use internal 8MHz oscillator directly */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_DIV) |
GCLK_GENDIV_ID(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_ID(0));
#endif
/* make sure we synchronize clock generator 0 before we go on */
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* Setup Clock generator 2 with divider 1 (32.768kHz) */
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_RUNSTDBY |
GCLK_GENCTRL_SRC_OSCULP32K);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* redirect all peripherals to a disabled clock generator (7) by default */
for (int i = 0x3; i <= 0x22; i++) {
GCLK->CLKCTRL.reg = ( GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN_GCLK7 );
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
}
// ****************************************************************************
void HAL_hardware_init(bool is_servo_reader, bool servo_output_enabled, bool uart_output_enabled)
{
uint32_t *coarse_p;
uint32_t coarse;
// FIXME: output diagnostics on UART only if uart_output_enabled is false
(void) uart_output_enabled;
// ------------------------------------------------
// Perform GPIO initialization as early as possible
HAL_gpio_set(HAL_GPIO_BLANK);
HAL_gpio_out(HAL_GPIO_BLANK);
HAL_gpio_clear(HAL_GPIO_SWITCHED_LIGHT_OUTPUT);
HAL_gpio_out(HAL_GPIO_SWITCHED_LIGHT_OUTPUT);
HAL_gpio_out(HAL_GPIO_XLAT);
HAL_gpio_out(HAL_GPIO_SIN);
HAL_gpio_pmuxen(HAL_GPIO_SIN);
HAL_gpio_out(HAL_GPIO_SCK);
HAL_gpio_pmuxen(HAL_GPIO_SCK);
HAL_gpio_in(HAL_GPIO_CH3);
HAL_gpio_pmuxen(HAL_GPIO_CH3);
HAL_gpio_in(HAL_GPIO_PUSH_BUTTON);
HAL_gpio_pmuxen(HAL_GPIO_USB_DM);
HAL_gpio_pmuxen(HAL_GPIO_USB_DP);
// Turn the status LED on to signify we are initializing
HAL_gpio_out(HAL_GPIO_LED);
HAL_gpio_out(HAL_GPIO_LED2);
HAL_gpio_set(HAL_GPIO_LED);
HAL_gpio_set(HAL_GPIO_LED2);
// ------------------------------------------------
// Configure GPIOs shared between servo inputs, servo output and UART
// Output UART Tx on OUT in all cases when the servo output is disabled
if (servo_output_enabled) {
HAL_gpio_out(HAL_GPIO_OUT);
HAL_gpio_pmuxen(HAL_GPIO_OUT);
}
else {
HAL_gpio_out(HAL_GPIO_TX_ON_OUT);
HAL_gpio_pmuxen(HAL_GPIO_TX_ON_OUT);
tx_pad = HAL_GPIO_TX_ON_OUT.txpo;
}
if (is_servo_reader) {
HAL_gpio_in(HAL_GPIO_ST);
HAL_gpio_pmuxen(HAL_GPIO_ST);
HAL_gpio_in(HAL_GPIO_TH);
HAL_gpio_pmuxen(HAL_GPIO_TH);
}
else {
HAL_gpio_in(HAL_GPIO_RX);
HAL_gpio_pmuxen(HAL_GPIO_RX);
// In case we have a UART and a servi output, TH is unused. We can
// use TH as Tx signal, just like in the LPC812 Mk4 light controller
if (servo_output_enabled) {
HAL_gpio_out(HAL_GPIO_TX_ON_TH);
HAL_gpio_pmuxen(HAL_GPIO_TX_ON_TH);
tx_pad = HAL_GPIO_TX_ON_TH.txpo;
}
else {
HAL_gpio_in(HAL_GPIO_TH);
HAL_gpio_pmuxen(HAL_GPIO_TH);
}
}
// ------------------------------------------------
// Since we intend to run at 48 MHz system clock, we neeed to conigure
// one wait state for the flash according to the datasheet.
NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS(1);
// ------------------------------------------------
// Set up the PLL to provide a 48 MHz system clock
SYSCTRL->INTFLAG.reg =
SYSCTRL_INTFLAG_BOD33RDY |
SYSCTRL_INTFLAG_BOD33DET |
SYSCTRL_INTFLAG_DFLLRDY;
SYSCTRL->DFLLCTRL.reg = 0;
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL(48000);
// Load PLL calibration values from NVRAM
coarse_p = (uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR;
coarse = (*coarse_p & FUSES_DFLL48M_COARSE_CAL_Msk) >> FUSES_DFLL48M_COARSE_CAL_Pos;
SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(512);
SYSCTRL->DFLLCTRL.reg =
SYSCTRL_DFLLCTRL_ENABLE |
SYSCTRL_DFLLCTRL_USBCRM |
SYSCTRL_DFLLCTRL_BPLCKC |
SYSCTRL_DFLLCTRL_STABLE |
SYSCTRL_DFLLCTRL_CCDIS;
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));
// ------------------------------------------------
// Reset the generic clock control block
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
// Setup GENCLK0 to run at 48 MHz. This clock is used for high speed
// peripherals such as SPI, USB and UART
GCLK->GENDIV.reg =
GCLK_GENDIV_ID(0) |
GCLK_GENDIV_DIV(1);
GCLK->GENCTRL.reg =
GCLK_GENCTRL_ID(0) |
GCLK_GENCTRL_SRC_DFLL48M |
GCLK_GENCTRL_RUNSTDBY |
GCLK_GENCTRL_GENEN;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
// Setup GENCLK1 to run at 2 MHz. We use GENCLK1 for timers that need
// microsecond resolution (e.g. servo output and servo reader).
// We derive the clock from the 48 MHz PLL, so we use a clock divider of
// 24
GCLK->GENDIV.reg =
GCLK_GENDIV_ID(1) |
GCLK_GENDIV_DIV(24);
GCLK->GENCTRL.reg =
GCLK_GENCTRL_ID(1) |
GCLK_GENCTRL_SRC_DFLL48M |
GCLK_GENCTRL_RUNSTDBY |
GCLK_GENCTRL_GENEN;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
// ------------------------------------------------
// Turn on power to the peripherals we use
PM->APBCMASK.reg =
UART_SERCOM_APBCMASK |
SPI_SERCOM_APBCMASK |
PM_APBAMASK_EIC |
PM_APBCMASK_EVSYS |
PM_APBCMASK_TCC0 |
PM_APBCMASK_TC4 |
PM_APBBMASK_USB;
// ------------------------------------------------
// Initialize the Event System
// Use GLKGEN0 (48 MHz) as clock source for the EVSYS0..2
GCLK->CLKCTRL.reg =
GCLK_CLKCTRL_ID_EVSYS_0 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN(0);
GCLK->CLKCTRL.reg =
GCLK_CLKCTRL_ID_EVSYS_1 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN(0);
GCLK->CLKCTRL.reg =
GCLK_CLKCTRL_ID_EVSYS_2 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN(0);
// Always turn on the Generic Clock within EVSYS
EVSYS->CTRL.reg = EVSYS_CTRL_GCLKREQ;
// ------------------------------------------------
// Configure the SYSTICK to create an interrupt every 1 millisecond
SysTick_Config(48000);
NVIC_SetPriority(SysTick_IRQn, 0);
// ------------------------
// The UART Tx can be used for diagnostics output if it is not in use.
// The pin is in use when HAL gets passed "uart_output_enabled==true"
// (UART used for pre-processor, winch or slave output), or when we
// have a servo reader and the servo output is enabled.
//
// Or in other words: the UART can output diagnostics on the OUT pin
// when it is not in use, or the UART can output diagnostics on the TH/Tx
// pin when we the UART reader is in use and no UART output function is
// configured.
diagnostics_on_uart = !uart_output_enabled;
if (is_servo_reader) {
if (servo_output_enabled) {
diagnostics_on_uart = false;
}
}
__enable_irq();
}
