static void _vip_hw_set_clock(int module, struct nxp_backward_camera_platform_data *param, bool on)
{
if (on) {
volatile u32 *clkgen_base = (volatile u32 *)IO_ADDRESS(NX_CLKGEN_GetPhysicalAddress(NX_VIP_GetClockNumber(module)));
NX_CLKGEN_SetBaseAddress(NX_VIP_GetClockNumber(module), (U32)clkgen_base);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
NX_CLKGEN_SetClockBClkMode(NX_VIP_GetClockNumber(module), NX_BCLKMODE_DYNAMIC);
/* printk("RSTCON Base: 0x%x\n", NX_RSTCON_GetBaseAddress()); */
/* printk("RSTCON VIP %d Reset Number %d, REG Number %d\n", module, NX_VIP_GetResetNumber(module), NX_VIP_GetResetNumber(module)>>5); */
/* printk("CLKGEN Base: 0x%x\n", clkgen_base); */
NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nDISABLE);
NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nENABLE);
if (param->is_mipi) {
printk("%s: apply mipi csi clock!!!\n", __func__);
NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 2); /* external PCLK */
NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 2);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
} else {
NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 4 + param->port); /* external PCLK */
NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 1);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
}
printk("VIP CLK GEN VAL: 0x%x\n", *clkgen_base);
NX_VIP_SetBaseAddress(module, IO_ADDRESS(NX_VIP_GetPhysicalAddress(module)));
}
}
int board_late_init(void)
{
#if defined(CONFIG_SYS_MMC_BOOT_DEV)
char boot[16];
sprintf(boot, "mmc dev %d", CONFIG_SYS_MMC_BOOT_DEV);
run_command(boot, 0);
#endif
#if defined CONFIG_RECOVERY_BOOT
if (RECOVERY_SIGNATURE == readl(SCR_RESET_SIG_READ)) {
writel((-1UL), SCR_RESET_SIG_RESET); /* clear */
printf("RECOVERY BOOT\n");
bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1);
run_command(CONFIG_CMD_RECOVERY_BOOT, 0); /* recovery boot */
}
writel((-1UL), SCR_RESET_SIG_RESET);
#endif /* CONFIG_RECOVERY_BOOT */
#if defined(CONFIG_BAT_CHECK)
{
int ret =0;
int bat_check_skip = 0;
// psw0523 for cts
// bat_check_skip = 1;
#if defined(CONFIG_DISPLAY_OUT)
ret = power_battery_check(bat_check_skip, bd_display_run);
#else
ret = power_battery_check(bat_check_skip, NULL);
#endif
if(ret == 1)
auto_update(UPDATE_KEY, UPDATE_CHECK_TIME);
}
#else /* CONFIG_BAT_CHECK */
// mipi reset
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_CSI, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nENABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nENABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nENABLE);
NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nENABLE);
// ac97 reset
NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nENABLE);
// scaler reset
NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nENABLE);
// pdm reset
NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_PDM_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always
NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nENABLE);
// mpegtsi reset
NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nENABLE);
// crypto reset
NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_CRYPTO_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always
NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nENABLE);
// spi1 reset
NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nENABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nENABLE);
// spi2 reset
NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nENABLE);
NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nENABLE);
// vip 0/1 reset
NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP0_MODULE, NX_BCLKMODE_DYNAMIC);
NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP0_MODULE, CTRUE);
NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nENABLE);
NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP1_MODULE, NX_BCLKMODE_DYNAMIC);
NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP1_MODULE, CTRUE);
NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nDISABLE);
NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nENABLE);
#if defined(CONFIG_DISPLAY_OUT)
bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1);
#endif
#ifdef CONFIG_CMD_NET
bd_eth_init();
#endif
/* Temp check gpio to update */
auto_update(UPDATE_KEY, UPDATE_CHECK_TIME);
#endif /* CONFIG_BAT_CHECK */
return 0;
}