//------------------------------------------------------------------------------
//
// Function: OEMInitDebugSerial
//
// Initializes the debug serial port
//
VOID OEMInitDebugSerial()
{
UINT32 DivSlot;
UINT32 uPCLK;
float Div;
// Map SFR Address
//
if (g_pUARTReg == NULL)
{
// UART0
g_pUARTReg = (S3C6410_UART_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_UART0, FALSE);
}
if (g_pGPIOReg == NULL)
{
g_pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
}
if (g_pSysConReg == NULL)
{
g_pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
}
// UART I/O port initialize
// UART0 Clock Enable
g_pSysConReg->PCLK_GATE |= (1<<1); // UART0
g_pSysConReg->SCLK_GATE |= (1<<5); // UART0~3
// UART0 Port Initialize (RXD0 : GPA0, TXD0: GPA1)
g_pGPIOReg->GPACON = (g_pGPIOReg->GPACON & ~(0xff<<0)) | (0x22<<0); // GPA0->RXD0, GPA1->TXD0
g_pGPIOReg->GPAPUD = (g_pGPIOReg->GPAPUD & ~(0xf<<0)) | (0x1<<0); // RXD0: Pull-down, TXD0: pull up/down disable
// Initialize UART
//
g_pUARTReg->ULCON = (0<<6)|(0<<3)|(0<<2)|(3<<0); // Normal Mode, No Parity, 1 Stop Bit, 8 Bit Data
g_pUARTReg->UCON = (0<<10)|(1<<9)|(1<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0); // PCLK divide, Polling Mode
g_pUARTReg->UFCON = (0<<6)|(0<<4)|(0<<2)|(0<<1)|(0<<0); // Disable FIFO
g_pUARTReg->UMCON = (0<<5)|(0<<4)|(0<<0); // Disable Auto Flow Control
uPCLK = System_GetPCLK();
Div = (float)((float)uPCLK/(16.0*(float)DEBUG_BAUDRATE)) - 1; //< S3C6410_PCLK is macro code defined in soc_cfg.h
DivSlot = (UINT32)((Div-(int)Div)*16);
g_pUARTReg->UBRDIV = (UINT32)Div; // Baud rate
g_pUARTReg->UDIVSLOT = aSlotTable[DivSlot];
}
/*
@func BOOL | InitEthDevice | Initializes the Ethernet device to be used for download.
@rdesc TRUE = Success, FALSE = Failure.
@comm
@xref
*/
BOOL InitEthDevice(PBOOT_CFG pBootCfg)
{
PBYTE pBaseIOAddress = NULL;
UINT32 MemoryBase = 0;
BOOL bResult = FALSE;
OALMSG(OAL_FUNC, (TEXT("+InitEthDevice.\r\n")));
InitSROMC_DM9000A();
// Use the MAC address programmed into flash by the user.
//
memcpy(pBSPArgs->kitl.mac, pBootCfg->EdbgAddr.wMAC, 6);
// Use the DM9000 Ethernet controller for download.
//
pfnEDbgInit = DM9000AInit;
pfnEDbgGetFrame = DM9000AGetFrame;
pfnEDbgSendFrame = DM9000ASendFrame;
pBaseIOAddress = (PBYTE)OALPAtoVA(pBSPArgs->kitl.devLoc.LogicalLoc, FALSE);
MemoryBase = (UINT32)OALPAtoVA(BSP_BASE_REG_PA_DM9000A_MEMBASE, FALSE);
// Initialize the Ethernet controller.
//
if (!pfnEDbgInit((PBYTE)pBaseIOAddress, MemoryBase, pBSPArgs->kitl.mac))
{
OALMSG(OAL_ERROR, (TEXT("ERROR: InitEthDevice: Failed to initialize Ethernet controller.\r\n")));
goto CleanUp;
}
// Make sure MAC address has been programmed.
//
if (!pBSPArgs->kitl.mac[0] && !pBSPArgs->kitl.mac[1] && !pBSPArgs->kitl.mac[2])
{
OALMSG(OAL_ERROR, (TEXT("ERROR: InitEthDevice: Invalid MAC address.\r\n")));
goto CleanUp;
}
bResult = TRUE;
CleanUp:
OALMSG(OAL_FUNC, (TEXT("-InitEthDevice.\r\n")));
return(bResult);
}
//------------------------------------------------------------------------------
//
// Function: OALIoCtlHalReboot
//
//
BOOL OALIoCtlHalReboot(UINT32 code, VOID *pInpBuffer,
UINT32 inpSize, VOID *pOutBuffer,
UINT32 outSize, UINT32 *pOutSize)
{
//
// If the board design supports software-controllable hardware reset logic, it should be
// used. Because this routine is specific to the S3C2450 CPU, it only uses the watchdog
// timer to assert reset. One downside to this approach is that nRSTOUT isn't asserted
// so any board-level logic isn't reset via this method. This routine can be overidden in
// the specific platform code to control board-level reset logic, should it exist.
//
volatile S3C2450_CLKPWR_REG *pCLKPWR = (S3C2450_CLKPWR_REG *)OALPAtoVA(S3C2450_BASE_REG_PA_CLOCK_POWER, FALSE);
//[david.modify] 2008-11-14 10:21
// lcpµØͼ¸´Î»
DPSTR_R1("reboot");
return ;
OALMSG(OAL_IOCTL&&OAL_FUNC, (L"+OALIoCtlHalReboot\r\n"));
// Into reset
pCLKPWR->SWRST = 0x533C2450;
// Wait for watchdog reset...
//
while(TRUE);
// Should never get to this point...
//
OALMSG(OAL_IOCTL&&OAL_FUNC, (L"-OALIoCtlHalReboot\r\n"));
return(TRUE);
}
static void InitializeCLKSource(void)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
OALMSG(TRUE, (L"[OAL] InitializeCLKSource()\r\n"));
pSysConReg->CLK_SRC = (pSysConReg->CLK_SRC & ~(0xFFFFFFF0))
|(0<<31) // TV27_SEL -> 27MHz
|(0<<30) // DAC27 -> 27MHz
|(0<<28) // SCALER_SEL -> MOUT_EPLL
|(1<<26) // LCD_SEL -> Dout_MPLL
|(0<<24) // IRDA_SEL -> MOUT_EPLL
|(0<<22) // MMC2_SEL -> MOUT_EPLL
|(0<<20) // MMC1_SEL -> MOUT_EPLL
|(0<<18) // MMC0_SEL -> MOUT_EPLL
|(0<<16) // SPI1_SEL -> MOUT_EPLL
|(0<<14) // SPI0_SEL -> MOUT_EPLL
|(0<<13) // UART_SEL -> MOUT_EPLL
|(0<<10) // AUDIO1_SEL -> MOUT_EPLL
|(0<<7) // AUDIO0_SEL -> MOUT_EPLL
|(0<<5) // UHOST_SEL -> 48MHz
|(0<<4); // MFCCLK_SEL -> HCLKx2 (0:HCLKx2, 1:MoutEPLL)
// TODO: What Clock need dividing???
pSysConReg->CLK_DIV0 = (pSysConReg->CLK_DIV0 & ~(0xf<<28))
| ((2-1)<<28); // MFCCLK = SRC/2
//pSysConReg->CLK_DIV1;
//pSysConReg->CLK_DIV2;
}
static void InitializeRTC(void)
{
volatile S3C6410_RTC_REG *pRTCReg = (S3C6410_RTC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_RTC, FALSE);
// As per the S3C6410 User Manual, the RTC clock divider should be reset for exact RTC operation.
// Enable RTC control first
pRTCReg->RTCCON |= (1<<0);
// Pulse the RTC clock divider reset
pRTCReg->RTCCON |= (1<<3);
pRTCReg->RTCCON &= ~(1<<3);
// The value of BCD registers in the RTC are undefined at reset. Set them to a known value
// pRTCReg->BCDSEC = 0;
// pRTCReg->BCDMIN = 0;
// pRTCReg->BCDHOUR = 0;
// pRTCReg->BCDDATE = 1;
// pRTCReg->BCDDAY = 1;
// pRTCReg->BCDMON = 1;
// pRTCReg->BCDYEAR = 0;
// Disable RTC control.
pRTCReg->RTCCON &= ~(1<<0);
}
void LTC3714_Init()
{
// We assume these GPIOs is used for only changing votage.
if(CHECK_IN_PA(LTC3714_Init))
{
// Assume call from startup.s in OAL
g_pGPIOReg = (S3C6410_GPIO_REG *)(S3C6410_BASE_REG_PA_GPIO);
}
else
{
OALMSG(TRUE, (_T("%s\r\n"), _T(__FUNCTION__)));
g_pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
}
//GPIO Setting - For LTC3714 VID
g_pGPIOReg->GPNCON = (g_pGPIOReg->GPNCON & ~(0x3ff<<22)) | (0x155<<22);
// Pull-up/dn disable
g_pGPIOReg->GPNPUD = (g_pGPIOReg->GPNPUD & ~(0x3ff<<22));
// Latch Control Signal
// CORE_REG_OE: XhiA9(GPL9), ARM_REG_LE: XhiA8(GPL8), INT_REG_LE: XhiA10(GPL10)
g_pGPIOReg->GPLCON1 = (g_pGPIOReg->GPLCON1 & ~(0xfff)) | (0x111);
g_pGPIOReg->GPLPUD = (g_pGPIOReg->GPLPUD & ~(0x3f<<16));
}
void OEMSWReset(void)
{
//
// If the board design supports software-controllable hardware reset logic, it should be
// used. Because this routine is specific to the S3C6410 CPU, it only uses the watchdog
// timer to assert reset. One downside to this approach is that nRSTOUT isn't asserted
// so any board-level logic isn't reset via this method. This routine can be overidden in
// the specific platform code to control board-level reset logic, should it exist.
//
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
OALMSG(TRUE, (L"[OEM] ++OEMSWReset()\r\n"));
// HCLK_IROM, HCLK_MEM1, HCLK_MEM0, HCLK_MFC Should be Always On for power Mode (Something coupled with BUS operation)
pSysConReg->HCLK_GATE |= ((1<<25)|(1<<22)|(1<<21)|(1<<0));
OALMSG(TRUE, (L"[OEM] + OEMSWReset() using watchdog timer\r\n"));
// Generate Software Reset using watchdog timer
_OEMSWReset();
// Wait for Reset
//
while(1);
// Should Never Get Here
//
OALMSG(TRUE, (L"[OEM] --OEMSWReset() : Do Not See Me !!!!!! \r\n"));
}
BOOL OEMKitlStartup(void)
{
OAL_KITL_ARGS KITLArgs;
OAL_KITL_ARGS *pKITLArgs;
BOOL bRet = FALSE;
UCHAR *szDeviceId,buffer[OAL_KITL_ID_SIZE]="\0";
OALMSG(OAL_KITL&&OAL_FUNC, (L"[KITL] ++OEMKitlStartup()\r\n"));
// Look for bootargs left by the bootloader or left over from an earlier boot.
//
pKITLArgs = (OAL_KITL_ARGS *)OALArgsQuery(OAL_ARGS_QUERY_KITL);
szDeviceId = (UCHAR*)OALArgsQuery(OAL_ARGS_QUERY_DEVID);
// If no KITL arguments were found (typically provided by the bootloader), then select
// some default settings.
//
if (pKITLArgs == NULL)
{
memset(&KITLArgs, 0, sizeof(OAL_KITL_ARGS));
// By default, enable KITL and use USB Serial
KITLArgs.flags |= OAL_KITL_FLAGS_ENABLED;
KITLArgs.devLoc.IfcType = Internal;
KITLArgs.devLoc.BusNumber = 0;
KITLArgs.devLoc.PhysicalLoc = (PVOID)S3C6410_BASE_REG_PA_USBOTG_LINK;
KITLArgs.devLoc.LogicalLoc = (DWORD)KITLArgs.devLoc.PhysicalLoc;
pKITLArgs = &KITLArgs;
}
if (pKITLArgs->devLoc.LogicalLoc == BSP_BASE_REG_PA_DM9000A_IOBASE)
{
// Ethernet specific initialization
//configure chipselect for DM9000A
InitSROMC_DM9000A();
//setting EINT7 as IRQ_LAN
if (!(pKITLArgs->flags & OAL_KITL_FLAGS_POLL))
{
g_pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
}
// Setup pointers to the power on and power off functions to enable KITL
// functionality across suspend/resume
// Modify the g_kitlEthCS8900A structure defined in kitl_cfg.h
g_kitlEthDM9000A.pfnPowerOff = (OAL_KITLETH_POWER_OFF)BSPKitlEthPowerOff;
g_kitlEthDM9000A.pfnPowerOn = (OAL_KITLETH_POWER_ON)BSPKitlEthPowerOn;
}
bRet = OALKitlInit ((LPCSTR)szDeviceId, pKITLArgs, g_kitlDevices);
OALMSG(OAL_KITL&&OAL_FUNC, (L"[KITL] --OEMKitlStartup() = %d\r\n", bRet));
return bRet;
}
void InitializeDVS(void)
{
if(!g_bBSP_DVSEN)
{
return;
}
g_pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
g_pOTGLinkReg = (unsigned int *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_LINK, FALSE);
g_CurrentLevel = SYS_L0; // Initial System Level
#ifdef ENABLE_VOLTAGE_CONTROL
PMIC_Init();
// This is caused by SMDK board bug. You can erase this line if you use the other board.
// PMIC_VoltageSet(SETVOLTAGE_BOTH, VoltageARM(g_CurrentLevel), 0);
#endif
}
void InitPowerCTL()
{
DWORD *powerCTL;
volatile S3C6410_GPIO_REG *pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
powerCTL = (DWORD *)OALArgsQuery(BSP_ARGS_QUERY_POWERCTL);
PWRCTL_InitializePowerCTL(powerCTL,pGPIOReg);
}
//------------------------------------------------------------------------------
//
// Function: OEMSetRealTime
//
// Updates the RTC with the specified system time.
//
BOOL OEMSetRealTime(LPSYSTEMTIME pTime)
{
BOOL rc = FALSE;
volatile S3C6400_RTC_REG *pRTCReg;
if (pTime == NULL) goto cleanUp;
OALMSG(OAL_RTC&&OAL_FUNC, (
L"+OEMSetRealTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wYear, pTime->wMonth, pTime->wDay, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds));
OALMSG(TRUE, (
L"OEMSetRealTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wYear, pTime->wMonth, pTime->wDay, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds));
// The RTC will only support a BCD year value of 0 - 99. The year datum is
// 1980, so any dates greater than 2079 will fail unless the datum is
// adjusted.
if ((pTime->wYear < RTC_YEAR_DATUM)
|| ((pTime->wYear - RTC_YEAR_DATUM) > 99))
{
OALMSG(OAL_ERROR, (L"ERROR: OEMSetRealTime: "
L"RTC cannot support a year greater than %d or less than %d "
L"(value %d)\r\n", (RTC_YEAR_DATUM + 99), RTC_YEAR_DATUM,
pTime->wYear));
goto cleanUp;
}
// Get uncached virtual address
pRTCReg = (S3C6400_RTC_REG *)OALPAtoVA(S3C6400_BASE_REG_PA_RTC, FALSE);
// Enable RTC control.
pRTCReg->RTCCON |= (1<<0);
pRTCReg->BCDSEC = TO_BCD(pTime->wSecond);
pRTCReg->BCDMIN = TO_BCD(pTime->wMinute);
pRTCReg->BCDHOUR = TO_BCD(pTime->wHour);
pRTCReg->BCDDATE = TO_BCD(pTime->wDay);
pRTCReg->BCDDAY = pTime->wDayOfWeek + 1;
pRTCReg->BCDMON = TO_BCD(pTime->wMonth);
pRTCReg->BCDYEAR = TO_BCD(pTime->wYear - RTC_YEAR_DATUM);
// Disable RTC control.
pRTCReg->RTCCON &= ~(1<<0);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMSetRealTime(rc = %d)\r\n", rc));
return rc;
}
static
UINT32
ReadFlashNK(
)
{
UINT32 rc = (UINT32)BL_ERROR;
ROMHDR *pTOC;
ULONG offset, size;
UCHAR *pData;
DWORD *pInfo;
UCHAR *pBase = OALPAtoVA(g_ulFlashBase, FALSE);
UCHAR *pStart = (void *)((UINT32)pBase + IMAGE_WINCE_NOR_OFFSET);
OALMSG(OAL_INFO, (L"\r\nLoad NK image from flash memory\r\n"));
// Set address where to place image
pData = (UCHAR*)IMAGE_WINCE_CODE_CA;
// First read 4kB with pointer to TOC
offset = 0;
size = 4096;
memcpy(pData + offset, pStart, size);
// Verify that we get CE image
pInfo = (DWORD *)(pData + offset + ROM_SIGNATURE_OFFSET);
if (*pInfo != ROM_SIGNATURE)
{
OALMSG(OAL_ERROR, (L"ERROR: Image signature not found\r\n"));
goto cleanUp;
}
// Read image up through actual TOC
offset = size;
size = pInfo[2] - size + sizeof(ROMHDR);
memcpy(pData + offset, pStart + offset, size);
// Verify image
if (!VerifyImage(pData, &pTOC))
{
OALMSG(OAL_ERROR, (L"ERROR: NK image doesn't have ROM signature\r\n"));
goto cleanUp;
}
// Read remainder of image
offset += size;
size = pTOC->physlast - pTOC->physfirst - offset;
memcpy(pData + offset, pStart + offset, size);
OALMSG(OAL_INFO, (L"NK Image Loaded\r\n"));
// Done
g_eboot.launchAddress = OALVAtoPA((UCHAR*)IMAGE_WINCE_CODE_CA);
rc = BL_JUMP;
cleanUp:
return rc;
}
BOOL
WriteFlashNK(
UINT32 address,
UINT32 size
)
{
BOOL rc = FALSE;
UCHAR *pData;
void *pBase = OALPAtoVA(g_ulFlashBase, FALSE);
void *pStart = (void *)((UINT32)pBase + IMAGE_WINCE_NOR_OFFSET);
OALLog(L"\r\nWriting NK image to flash memory\r\n");
// Get data location
pData = OEMMapMemAddr(address, address);
// Verify that we get CE image
if (!VerifyImage(pData, NULL))
{
OALMSG(OAL_ERROR, (L"ERROR: OEMWriteFlash: NK image signature not found\r\n"));
goto cleanUp;
}
// Unlock blocks
if (!OALFlashLock(pBase, pStart, size, FALSE))
{
OALMSG(OAL_ERROR, (L"ERROR: OEMWriteFlash: NK blocks could not be unlocked\r\n"));
goto cleanUp;
}
// Erase blocks
if (!OALFlashErase(pBase, pStart, size))
{
OALMSG(OAL_ERROR, (L"ERROR: OEMWriteFlash: NK blocks could not be erased\r\n"));
goto cleanUp;
}
// Write blocks
if (!OALFlashWrite(pBase, pStart, size, pData))
{
OALMSG(OAL_ERROR, (L"ERROR: OEMWriteFlash: NK blocks could not be written\r\n"));
goto cleanUp;
}
OALLog(L"NK image written\r\n");
// Change boot device to NOR
g_bootCfg.bootDevLoc.IfcType = Internal;
g_bootCfg.bootDevLoc.LogicalLoc = BSP_NOR_REGS_PA;
// Done
rc = TRUE;
cleanUp:
return rc;
}
VOID BSPPowerOff()
{
volatile S3C6410_GPIO_REG *pGPIOReg;
volatile S3C6410_ADC_REG *pADCReg;
volatile S3C6410_RTC_REG *pRTCReg;
volatile S3C6410_SYSCON_REG *pSysConReg;
OALMSG(OAL_FUNC, (TEXT("++BSPPowerOff()\n")));
OALMSG(1, (TEXT("++BSPPowerOff()\n")));
pGPIOReg = (S3C6410_GPIO_REG*)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
pADCReg = (S3C6410_ADC_REG*)OALPAtoVA(S3C6410_BASE_REG_PA_ADC, FALSE);
pRTCReg = (S3C6410_RTC_REG*)OALPAtoVA(S3C6410_BASE_REG_PA_RTC, FALSE);
pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
//-----------------------------
// Wait till NAND Erase/Write operation is finished
//-----------------------------
VFL_Sync();
//-----------------------------
// Disable DVS and Set to Full Speed
//-----------------------------
ChangeDVSLevel(SYS_L0);
// RTC Control Disable
pRTCReg->RTCCON = 0x0; // Subclk 32768 Hz, No Reset, Merged BCD counter, XTAL 2^-15, Control Disable
//-------------------------------
// GPIO Configuration for Sleep State
//-------------------------------
BSPConfigGPIOforPowerOff();
PWRCTL_Sleep();
//
//CLRPORT32(&pIOPort->GPGDAT, 1 << 4);
//----------------------------
// Wake Up Source Configuration
//----------------------------
S3C6410_WakeUpSource_Configure();
OALMSG(OAL_FUNC, (TEXT("--BSPPowerOff()\n")));
OALMSG(1, (TEXT("--BSPPowerOff()\n")));
}
static void InitializeINFORMSFR(void)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
OALMSG(TRUE, (L"[OAL] ++InitializeINFORMSFR()\r\n"));
pSysConReg->INFORM0 = 0x64100000;
OALMSG(TRUE, (L"[OAL] --InitializeINFORMSFR()\r\n"));
}
//--------------------------------------------------------------------
//48MHz clock source for usb host1.1, IrDA, hsmmc, spi is shared with otg phy clock.
//So, initialization and reset of otg phy shoud be done on initial booting time.
//--------------------------------------------------------------------
void InitializeOTGCLK(void)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
volatile OTG_PHY_REG *pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);
pSysConReg->HCLK_GATE |= (1<<20);
pSysConReg->OTHERS |= (1<<16);
pOtgPhyReg->OPHYPWR = 0x0; // OTG block, & Analog bock in PHY2.0 power up, normal operation
pOtgPhyReg->OPHYCLK = 0x20; // Externel clock/oscillator, 48MHz reference clock for PLL
pOtgPhyReg->ORSTCON = 0x1;
OALStall_ms(1);
pOtgPhyReg->ORSTCON = 0x0;
OALStall_ms(1);
pSysConReg->HCLK_GATE &= ~(1<<20);
}
//------------------------------------------------------------------------------
//
// Function: OEMGetRealTime
//
// Reads the current RTC value and returns a system time.
//
BOOL OEMGetRealTime(SYSTEMTIME *pTime)
{
volatile S3C6410_RTC_REG *pRTCReg;
UINT16 seconds;
BOOL rc = FALSE;
BOOL csEnter;
/* can get called before IoctlHalInitRTC, if so then don't try to
enter (uninitialized) cs (kernel should be single-proc, single-threaded here) */
if (g_oalRTCcsInit)
{
EnterCriticalSection(&g_oalRTCcs);
csEnter = TRUE;
}
else
csEnter = FALSE;
OALMSG(OAL_RTC&&OAL_FUNC, (L"+OEMGetRealTime(pTime = 0x%x)\r\n", pTime));
if (pTime == NULL) goto cleanUp;
// Get uncached virtual address
pRTCReg = (S3C6410_RTC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_RTC, FALSE);
// Enable RTC control.
pRTCReg->RTCCON |= (1<<0);
do
{
seconds = FROM_BCD(pRTCReg->BCDSEC & 0x7f);
pTime->wYear = FROM_BCD((pRTCReg->BCDYEAR & 0xff)) + RTC_YEAR_DATUM;
pTime->wMonth = FROM_BCD(pRTCReg->BCDMON & 0x1f);
pTime->wDay = FROM_BCD(pRTCReg->BCDDATE & 0x3f);
pTime->wDayOfWeek = pRTCReg->BCDDAY - 1;
pTime->wHour = FROM_BCD(pRTCReg->BCDHOUR & 0x3f);
pTime->wMinute = FROM_BCD(pRTCReg->BCDMIN & 0x7f);
pTime->wSecond = FROM_BCD(pRTCReg->BCDSEC & 0x7f);
pTime->wMilliseconds= 0;
} while (pTime->wSecond != seconds);
// Disable RTC control.
pRTCReg->RTCCON &= ~(1<<0);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMGetRealTime(rc = %d)\r\n", rc));
if (csEnter)
LeaveCriticalSection(&g_oalRTCcs);
return rc;
}
static void InitSROMC_DM9000A(void)
{
volatile S3C6410_SROMCON_REG *s6410SROM = (S3C6410_SROMCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SROMCON, FALSE);
s6410SROM->SROM_BW = (s6410SROM->SROM_BW & ~(0xF<<4)) |
//(1<<7)| // nWBE/nBE(for UB/LB) control for Memory Bank1(0=Not using UB/LB, 1=Using UB/LB)
//(1<<6)| // Wait enable control for Memory Bank1 (0=WAIT disable, 1=WAIT enable)
(1<<4); // Data bus width control for Memory Bank1 (0=8-bit, 1=16-bit)
s6410SROM->SROM_BC1 = ((DM9000A_Tacs<<28)+(DM9000A_Tcos<<24)+(DM9000A_Tacc<<16)+(DM9000A_Tcoh<<12)\
+(DM9000A_Tah<<8)+(DM9000A_Tacp<<4)+(DM9000A_PMC));
}
UINT32 System_GetAPLLCLK()
{
volatile S3C6410_SYSCON_REG *pSysConReg;
UINT32 APLLCLK;
pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
if(pSysConReg->CLK_SRC & 0x1) // APLL CLOCK SELECT
{
APLLCLK = ((FIN_CLK>>PLL_SVAL(pSysConReg->APLL_CON))/PLL_PVAL(pSysConReg->APLL_CON)*PLL_MVAL(pSysConReg->APLL_CON));
}
//------------------------------------------------------------------------------
//
// Function: OEMSetAlarmTime
//
// Set the RTC alarm time.
//
BOOL OEMSetAlarmTime(SYSTEMTIME *pTime)
{
BOOL rc = FALSE;
volatile S3C6400_RTC_REG *pRTCReg;
UINT32 irq;
if (pTime == NULL) goto cleanUp;
OALMSG(OAL_RTC&&OAL_FUNC, (
L"+OEMSetAlarmTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wMonth, pTime->wDay, pTime->wYear, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds));
OALMSG(TRUE, (
L"+OEMSetAlarmTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wMonth, pTime->wDay, pTime->wYear, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds));
// Get uncached virtual address
pRTCReg = (S3C6400_RTC_REG *)OALPAtoVA(S3C6400_BASE_REG_PA_RTC, FALSE);
// Enable RTC control
pRTCReg->RTCCON |= (1<<0);
pRTCReg->ALMSEC = TO_BCD(pTime->wSecond);
pRTCReg->ALMMIN = TO_BCD(pTime->wMinute);
pRTCReg->ALMHOUR = TO_BCD(pTime->wHour);
pRTCReg->ALMDATE = TO_BCD(pTime->wDay);
pRTCReg->ALMMON = TO_BCD(pTime->wMonth);
pRTCReg->ALMYEAR = TO_BCD(pTime->wYear - RTC_YEAR_DATUM);
// Enable the RTC Alarm
pRTCReg->RTCALM = 0x7f;
// Disable RTC control.
pRTCReg->RTCCON &= ~(1<<0);
// Clear RTC Alarm Interrupt Pending
pRTCReg->INTP |= (1<<1);
// Enable and Clear RTC Alarm Interrupt
irq = IRQ_RTC_ALARM;
OALIntrDoneIrqs(1, &irq);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMSetAlarmTime(rc = %d)\r\n", rc));
return rc;
}
UINT32 System_GetARMCLK()
{
UINT32 PLLCLK;
UINT32 ARMCLK;
volatile S3C6410_SYSCON_REG *pSysConReg;
pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
PLLCLK = System_GetAPLLCLK();
ARMCLK = PLLCLK/ARMDIV(pSysConReg->CLK_DIV0);
return ARMCLK;
}
//--------------------------------------------------------------------
//48MHz clock source for usb host1.1, IrDA, hsmmc, spi is shared with otg phy clock.
//So, initialization and reset of otg phy shoud be done on initial booting time.
//--------------------------------------------------------------------
static void ControlOTGCLK(BOOL OnOff)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
volatile OTG_PHY_REG *pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);
if (OnOff)
{
pSysConReg->HCLK_GATE |= (1<<20);
pSysConReg->OTHERS |= (1<<16);
pOtgPhyReg->OPHYPWR = 0x0; // OTG block, & Analog bock in PHY2.0 power up, normal operation
pOtgPhyReg->OPHYCLK = 0x00; // Externel clock/oscillator, 48MHz reference clock for PLL
pOtgPhyReg->ORSTCON = 0x1;
Delay(100);
pOtgPhyReg->ORSTCON = 0x0;
Delay(100);
pSysConReg->HCLK_GATE &= ~(1<<20);
}
else
{
pOtgPhyReg->OPHYPWR = ((0x1<<4)|(0x1<<3)|(0x1<<0)); // OTG block, & Analog bock in PHY2.0 power down, force_suspend
}
}
BOOL InitKitlEtherArgs (OAL_KITL_ARGS *pKitlArgs)
{
// Initialize flags
pKitlArgs->flags = OAL_KITL_FLAGS_ENABLED | OAL_KITL_FLAGS_VMINI;
#ifdef CS8900A_KITL_POLLMODE
pKitlArgs->flags |= OAL_KITL_FLAGS_POLL;
#endif
#ifdef CS8900A_KITL_DHCP
pKitlArgs->flags |= OAL_KITL_FLAGS_DHCP;
#endif
pKitlArgs->devLoc.IfcType = Internal;
pKitlArgs->devLoc.BusNumber = 0;
pKitlArgs->devLoc.LogicalLoc = BSP_BASE_REG_PA_CS8900A_IOBASE;
pKitlArgs->devLoc.Pin = 0;
OALKitlStringToMAC(CS8900A_MAC,pKitlArgs->mac);
#ifndef CS8900A_KITL_DHCP
pKitlArgs->ipAddress = OALKitlStringToIP(CS8900A_IP_ADDRESS);
pKitlArgs->ipMask = OALKitlStringToIP(CS8900A_IP_MASK);
pKitlArgs->ipRoute = OALKitlStringToIP(CS8900A_IP_ROUTER);
#endif
g_kitlDevice.name = L"6400Ethernet";
g_kitlDevice.ifcType = Internal;
g_kitlDevice.type = OAL_KITL_TYPE_ETH;
g_kitlDevice.pDriver = (void *)&g_kitlEthCS8900A;
//configure nCS3 for cs8900a
InitSROMC_CS8900();
//setting EINT10 as IRQ_LAN
if (!(pKitlArgs->flags & OAL_KITL_FLAGS_POLL))
{
g_pGPIOReg = (S3C6400_GPIO_REG *)OALPAtoVA(S3C6400_BASE_REG_PA_GPIO, FALSE);
g_pGPIOReg->GPNCON = (g_pGPIOReg->GPNCON & ~(0x3<<20)) | (0x2<<20);
g_pGPIOReg->GPGPUD = (g_pGPIOReg->GPGPUD & ~(0x3<<20)); // pull-up/down disable
g_pGPIOReg->EINT0CON0 = (g_pGPIOReg->EINT0CON0 & ~(0x7<<20)) | (0x1<<20); // High Level trigger
}
return TRUE;
}
static void InitializeBlockPower(void)
{
volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
OALMSG(OAL_FUNC, (L"[OAL] InitializeBlockPower()\r\n"));
pSysConReg->NORMAL_CFG = (1<<31) // Reserved
|(0<<30) // IROM Block Off (Internal 32KB Boot ROM)
|(0x1FFF<<17) // Reserved
|(1<<16) // DOMAIN_ETM On (JTAG not connected when ETM off)
|(0<<15) // DOMAIN_S Off (SDMA0, SDMA1, Security System)
|(1<<14) // DOMAIN_F On (LCD, Post, Rotator)
|(1<<13) // DOMAIN_P Off (TV Scaler, TV Encoder, 2D)
|(1<<12) // DOMAIN_I Off (Cam I/F, Jpeg)
|(0x3<<10) // Reserved
|(0<<9) // DOMAIN_V Off (MFC)
|(0x100); // Reserved
}
//------------------------------------------------------------------------------
//
// Function: OEMSetAlarmTime
//
// Set the RTC alarm time.
//
BOOL OEMSetAlarmTime(SYSTEMTIME *pTime)
{
BOOL rc = FALSE;
S3C2410X_RTC_REG *pRTCReg;
UINT32 irq;
OALMSG(OAL_RTC&&OAL_FUNC, (
L"+OEMSetAlarmTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wMonth, pTime->wDay, pTime->wYear, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds
));
if (pTime == NULL) goto cleanUp;
// Get uncached virtual address
pRTCReg = OALPAtoVA(S3C2410X_BASE_REG_PA_RTC, FALSE);
// Enable RTC control
SETREG32(&pRTCReg->RTCCON, 1);
OUTPORT32(&pRTCReg->ALMSEC, TO_BCD(pTime->wSecond));
OUTPORT32(&pRTCReg->ALMMIN, TO_BCD(pTime->wMinute));
OUTPORT32(&pRTCReg->ALMHOUR, TO_BCD(pTime->wHour));
OUTPORT32(&pRTCReg->ALMDATE, TO_BCD(pTime->wDay));
OUTPORT32(&pRTCReg->ALMMON, TO_BCD(pTime->wMonth));
OUTPORT32(&pRTCReg->ALMYEAR, TO_BCD(pTime->wYear - RTC_YEAR_DATUM));
// Enable the RTC alarm interrupt
OUTPORT32(&pRTCReg->RTCALM, 0x7F);
// Disable RTC control.
CLRREG32(&pRTCReg->RTCCON, 1);
// Enable/clear RTC interrupt
irq = IRQ_RTC;
OALIntrDoneIrqs(1, &irq);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMSetAlarmTime(rc = %d)\r\n", rc));
return rc;
}
//////////
// Function Name : OTGDevice_InitOtg
// Function Desctiption : This function initializes OTG PHY and LINK.
// Input : NONE
// Output : NONE
// Version :
void OTGDevice_Init()
{
UINT8 ucMode;
volatile S3C6410_SYSCON_REG *g_pSysConReg;
USBDBGMSG(USBDBG_ZONE_FUNC, (L"usbpdd: +OTGDevice_Init\r\n"));
g_pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
// Enable Clock Source
g_pSysConReg->HCLK_GATE |= (1<<20); // HCLK_USB
#ifdef OTGDEVICE_HIGH_SPEED
USBDBGMSG(USBDBG_ZONE_VERBOSE, (L"usbpdd: Init: Running as High Speed device by default\r\n"));
oOtgDev.m_eSpeed = USB_HIGH;
oOtgDev.m_uControlEPMaxPktSize = HIGH_SPEED_CONTROL_PKT_SIZE;
oOtgDev.m_uBulkInEPMaxPktSize = HIGH_SPEED_BULK_PKT_SIZE;
oOtgDev.m_uBulkOutEPMaxPktSize = HIGH_SPEED_BULK_PKT_SIZE;
#else
USBDBGMSG(USBDBG_ZONE_VERBOSE, (L"usbpdd: Init: Running as Full Speed device by default\r\n"));
oOtgDev.m_eSpeed = USB_FULL;
oOtgDev.m_uControlEPMaxPktSize = FULL_SPEED_CONTROL_PKT_SIZE;
oOtgDev.m_uBulkInEPMaxPktSize = FULL_SPEED_BULK_PKT_SIZE;
oOtgDev.m_uBulkOutEPMaxPktSize = FULL_SPEED_BULK_PKT_SIZE;
#endif
oOtgDev.m_uIsUsbOtgSetConfiguration = 0;
OTGDevice_SetSoftDisconnect();
OTGDevice_SoftResetCore();
OTGDevice_InitCore();
OTGDevice_CheckCurrentMode(&ucMode);
if (ucMode == INT_DEV_MODE)
{
OTGDevice_StallHelper(4000);
OTGDevice_InitDevice();
}
else
{
USBDBGMSG(USBDBG_ZONE_ERROR, (L"usbpdd: Error! OTGDevice_Init: Current Mode is Host\r\n"));
return;
}
}
UINT32 System_GetHCLK()
{
UINT32 HCLK;
UINT32 PLLCLK;
volatile S3C6410_SYSCON_REG *pSysConReg;
pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
if(System_VCheckSyncMode())
{
PLLCLK = System_GetAPLLCLK();
}
else
{
PLLCLK = System_GetMPLLCLK();
}
HCLK = PLLCLK/HCLKX2DIV(pSysConReg->CLK_DIV0)/HCLKDIV(pSysConReg->CLK_DIV0);
return HCLK;
}
/*
@func BOOL | OEMGetRealTime | Returns the current wall-clock time from the RTC.
@rdesc TRUE = Success, FALSE = Failure.
@comm
@xref
*/
static BOOL OEMGetRealTime(LPSYSTEMTIME lpst)
{
volatile S3C6410_RTC_REG *s6410RTC = (S3C6410_RTC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_RTC, FALSE);
do
{
lpst->wYear = FROM_BCD(s6410RTC->BCDYEAR) + 2000 ;
lpst->wMonth = FROM_BCD(s6410RTC->BCDMON & 0x1f);
lpst->wDay = FROM_BCD(s6410RTC->BCDDATE & 0x3f);
lpst->wDayOfWeek = (s6410RTC->BCDDAY - 1);
lpst->wHour = FROM_BCD(s6410RTC->BCDHOUR & 0x3f);
lpst->wMinute = FROM_BCD(s6410RTC->BCDMIN & 0x7f);
lpst->wSecond = FROM_BCD(s6410RTC->BCDSEC & 0x7f);
lpst->wMilliseconds = 0;
}
while (!(lpst->wSecond));
return(TRUE);
}
//------------------------------------------------------------------------------
//
// Function: OEMGetRealTime
//
// Reads the current RTC value and returns a system time.
//
BOOL OEMGetRealTime(SYSTEMTIME *pTime)
{
volatile S3C6400_RTC_REG *pRTCReg;
UINT16 seconds;
BOOL rc = FALSE;
OALMSG(OAL_RTC&&OAL_FUNC, (L"+OEMGetRealTime(pTime = 0x%x)\r\n", pTime));
if (pTime == NULL) goto cleanUp;
// Get uncached virtual address
pRTCReg = (S3C6400_RTC_REG *)OALPAtoVA(S3C6400_BASE_REG_PA_RTC, FALSE);
// Enable RTC control.
pRTCReg->RTCCON |= (1<<0);
do
{
seconds = FROM_BCD(pRTCReg->BCDSEC & 0x7f);
pTime->wYear = FROM_BCD(pRTCReg->BCDYEAR & 0xff) + RTC_YEAR_DATUM;
pTime->wMonth = FROM_BCD(pRTCReg->BCDMON & 0x1f);
pTime->wDay = FROM_BCD(pRTCReg->BCDDATE & 0x3f);
pTime->wDayOfWeek = pRTCReg->BCDDAY - 1;
pTime->wHour = FROM_BCD(pRTCReg->BCDHOUR & 0x3f);
pTime->wMinute = FROM_BCD(pRTCReg->BCDMIN & 0x7f);
pTime->wSecond = FROM_BCD(pRTCReg->BCDSEC & 0x7f);
pTime->wMilliseconds = 0;
} while (pTime->wSecond != seconds);
// Disable RTC control.
pRTCReg->RTCCON &= ~(1<<0);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMGetRealTime(rc = %d)\r\n", rc));
return rc;
}
//------------------------------------------------------------------------------
//
// Function: OEMProfileTimerEnable
//
// This function is called by kernel to start kernel profiling timer.
//
VOID OEMProfileTimerEnable(DWORD interval)
{
BOOL enabled;
UINT32 irq;
OALMSG(TRUE, (L"+OEMProfileTimerEnable(%d)\r\n", interval));
// We can't enable timer second time
if (g_profiler.enabled) return;
// Obtain a pointer to the PWM registers.
if (!g_pPWMRegs)
{
g_pPWMRegs = (S3C2450_PWM_REG *) OALPAtoVA(S3C2450_BASE_REG_PA_PWM, FALSE);
}
// How many hi-res ticks per profiler hit
g_profiler.countsPerHit = (g_oalTimer.countsPerMSec * interval)/1000;
// Following code should not be interrupted
enabled = INTERRUPTS_ENABLE(FALSE);
// Configure profiling ISR callback function.
g_pProfilerISR = OALProfileIntrHandler;
// Update the compare register for the next profile hit.
ConfigureNextProfilerCount(g_profiler.countsPerHit);
// Enable interrupts
INTERRUPTS_ENABLE(enabled);
irq = IRQ_TIMER2;
OALIntrDoneIrqs(1, &irq);
// Set flag
g_profiler.enabled = TRUE;
OALMSG(TRUE, (L"-OEMProfileTimerEnable\r\n"));
}
