/*ARGSUSED*/
static int
fm801_audio_prepare_for_output (int dev, int bsize, int bcount)
{
fm801_devc *devc = audio_engines[dev]->devc;
fm801_portc *portc = audio_engines[dev]->portc;
dmap_t *dmap = audio_engines[dev]->dmap_out;
unsigned short value;
unsigned char frequency;
oss_native_word flags;
MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
value = 0x0000;
if (portc->channels > 1)
value |= 0x8000;
if (portc->bits == 16)
value |= 0x4000;
frequency = sampling_rate (portc->speed);
value |= (frequency << 8);
if (portc->channels == 4)
value |= (1 << 12); /* 4channel output */
if (portc->channels == 6)
value |= (1 << 13); /* 6channel output */
OUTW (devc->osdev, value, devc->base + PLAY_CONTROL);
OUTW (devc->osdev, dmap->fragment_size - 1, devc->base + PLAY_SIZE);
OUTL (devc->osdev, dmap->dmabuf_phys, devc->base + PLAY_BUF1_ADDR);
OUTL (devc->osdev, dmap->dmabuf_phys + dmap->fragment_size,
devc->base + PLAY_BUF2_ADDR);
devc->play_flag = 1;
devc->play_count = 1;
portc->audio_enabled &= ~PCM_ENABLE_OUTPUT;
portc->trigger_bits &= ~PCM_ENABLE_OUTPUT;
MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
return 0;
}
static int lan_saa9730_start(struct lan_saa9730_private *lp)
{
lan_saa9730_buffer_init(lp);
/* Initialize Rx Buffer Index */
lp->NextRcvPacketIndex = 0;
lp->NextRcvToUseIsA = 1;
/* Set current buffer index & next available packet index */
lp->NextTxmPacketIndex = 0;
lp->NextTxmBufferIndex = 0;
lp->PendingTxmPacketIndex = 0;
lp->PendingTxmBufferIndex = 0;
OUTL(INL(&lp->lan_saa9730_regs->LanDmaCtl) | DMA_CTL_EN_TX_DMA |
DMA_CTL_EN_RX_DMA, &lp->lan_saa9730_regs->LanDmaCtl);
/* For Tx, turn on MAC then DMA */
OUTL(INL(&lp->lan_saa9730_regs->TxCtl) | TX_CTL_TX_EN,
&lp->lan_saa9730_regs->TxCtl);
/* For Rx, turn on DMA then MAC */
OUTL(INL(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN,
&lp->lan_saa9730_regs->RxCtl);
/* Set Ok2Use to let hardware owns the buffers */
OUTL(OK2USE_RX_A | OK2USE_RX_B | OK2USE_TX_A | OK2USE_TX_B,
&lp->lan_saa9730_regs->Ok2Use);
return 0;
}
static void evm_saa9730_disable_lan_int(struct lan_saa9730_private *lp)
{
OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT,
&lp->evm_saa9730_regs->InterruptBlock1);
OUTL(INL(&lp->evm_saa9730_regs->InterruptEnable1) & ~EVM_LAN_INT,
&lp->evm_saa9730_regs->InterruptEnable1);
}
static int
mdio_read(struct eth_device *dev, int phy_id, int addr)
{
int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
int i, retval = 0;
/* Shift the read command bits out. */
for (i = 15; i >= 0; i--) {
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
OUTL(dev, dataval, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
/* Read the two transition, 16 data, and wire-idle bits. */
for (i = 19; i > 0; i--) {
OUTL(dev, MDIO_EnbIn, EECtrl);
mdio_delay(EECtrl);
retval =
(retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
return (retval >> 1) & 0xffff;
}
static int lan_saa9730_stop(struct lan_saa9730_private *lp)
{
int i;
/* Stop DMA first */
OUTL(INL(&lp->lan_saa9730_regs->LanDmaCtl) &
~(DMA_CTL_EN_TX_DMA | DMA_CTL_EN_RX_DMA),
&lp->lan_saa9730_regs->LanDmaCtl);
/* Set the SW Reset bits in DMA and MAC control registers */
OUTL(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
OUTL(INL(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET,
&lp->lan_saa9730_regs->MacCtl);
/*
* Wait for MAC reset to have finished. The reset bit is auto cleared
* when the reset is done.
*/
i = 0;
while (INL(&lp->lan_saa9730_regs->MacCtl) & MAC_CONTROL_RESET) {
i++;
if (i > 100) {
printk
("Error: lan_sa9730_stop: MAC reset timeout\n");
return -1;
}
mdelay(1); /* wait 1 ms. */
}
return 0;
}
static void
ns8382x_init_rxd(struct eth_device *dev)
{
int i;
OUTL(dev, 0x0, RxRingPtrHi);
cur_rx = 0;
for (i = 0; i < NUM_RX_DESC; i++) {
rxd[i].link =
cpu_to_le32((i + 1 <
NUM_RX_DESC) ? (u32) & rxd[i +
1] : (u32) &
rxd[0]);
rxd[i].extsts = cpu_to_le32((u32) 0x0);
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
#ifdef NS8382X_DEBUG
printf
("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
i, &rxd[i], le32_to_cpu(rxd[i].link),
le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
#endif
}
OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
#ifdef NS8382X_DEBUG
printf("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
INL(dev, RxRingPtr));
#endif
}
static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp)
{
OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT,
&lp->evm_saa9730_regs->InterruptBlock1);
OUTL(INL(&lp->evm_saa9730_regs->InterruptStatus1) | EVM_LAN_INT,
&lp->evm_saa9730_regs->InterruptStatus1);
OUTL(INL(&lp->evm_saa9730_regs->InterruptEnable1) | EVM_LAN_INT |
EVM_MASTER_EN, &lp->evm_saa9730_regs->InterruptEnable1);
}
/* Function: ns8382x_reset
* Description: soft resets the controller chip
* Arguments: struct eth_device *dev: NIC data structure
* Returns: void.
*/
static void
ns8382x_reset(struct eth_device *dev)
{
OUTL(dev, ChipReset, ChipCmd);
while (INL(dev, ChipCmd))
/*wait until done */ ;
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
}
static void
ns8382x_disable(struct eth_device *dev)
{
/* Disable interrupts using the mask. */
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
/* Stop the chip's Tx and Rx processes. */
OUTL(dev, (RxOff | TxOff), ChipCmd);
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}
/* Generate the preamble required for initial synchronization and
a few older transceivers. */
static void
mdio_sync(struct eth_device *dev, u32 offset)
{
int bits = 32;
/* Establish sync by sending at least 32 logic ones. */
while (--bits >= 0) {
OUTL(dev, MDIO_WRITE1, offset);
mdio_delay(offset);
OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
mdio_delay(offset);
}
}
static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
{
/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
io_base_addr + bios_rom_addr);
/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
io_base_addr + bios_rom_addr);
}
/* Function: ns8382x_send
* Description: transmits a packet and waits for completion or timeout.
* Returns: void. */
static int
ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
{
u32 i, status = 0;
vu_long tx_stat = 0;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
#ifdef NS8382X_DEBUG
printf("ns8382x_send: sending %d bytes\n", (int)length);
#endif
/* set the transmit buffer descriptor and enable Transmit State Machine */
txd.link = cpu_to_le32(0x0);
txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
txd.extsts = cpu_to_le32(0x0);
txd.cmdsts = cpu_to_le32(DescOwn | length);
/* load Transmit Descriptor Register */
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
#ifdef NS8382X_DEBUG
printf("ns8382x_send: TX descriptor register loaded with: %#08X\n",
INL(dev, TxRingPtr));
printf("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
#endif
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
dev->name, tx_stat);
goto Done;
}
}
if (!(tx_stat & DescPktOK)) {
printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
goto Done;
}
#ifdef NS8382X_DEBUG
printf("ns8382x_send: tx_stat: %#08X\n", tx_stat);
#endif
status = 1;
Done:
return status;
}
static void
ns8382x_init_txd(struct eth_device *dev)
{
txd.link = (u32) 0;
txd.bufptr = cpu_to_le32((u32) & txb[0]);
txd.cmdsts = (u32) 0;
txd.extsts = (u32) 0;
OUTL(dev, 0x0, TxRingPtrHi);
OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
#ifdef NS8382X_DEBUG
printf("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
INL(dev, TxRingPtr), &txd);
#endif
}
static int
ac97_write (void *devc_, int index, int data)
{
oss_native_word access;
unsigned i, N;
unsigned char byte;
als300_devc *devc = devc_;
oss_native_word flags;
MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
i = 0;
N = 1000;
do
{
byte = INB (devc->osdev, devc->base + 6) & 0x80;
if (byte == 0x00)
goto go;
oss_udelay (10);
i++;
}
while (i < N);
if (i >= N)
cmn_err (CE_WARN, "\n Write AC97 mixer index time out !!");
go:
access = index;
access <<= 24; /*index */
access &= 0x7fffffff; /*write */
access |= data; /*data */
OUTL (devc->osdev, access, devc->base);
MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
return 0;
}
static int lan_saa9730_rx(struct net_device *dev)
{
struct lan_saa9730_private *lp =
(struct lan_saa9730_private *) dev->priv;
int len = 0;
struct sk_buff *skb = 0;
unsigned int rx_status;
int BufferIndex;
int PacketIndex;
unsigned int *pPacket;
unsigned char *pData;
if (lan_saa9730_debug > 5)
printk("lan_saa9730_rx interrupt\n");
/* Clear receive interrupts. */
OUTL(DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT |
DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus);
/* Address next packet */
if (lp->NextRcvToUseIsA)
BufferIndex = 0;
else
BufferIndex = 1;
PacketIndex = lp->NextRcvPacketIndex;
pPacket = (unsigned int *) lp->RcvBuffer[BufferIndex][PacketIndex];
rx_status = le32_to_cpu(*pPacket);
/* Process each packet. */
while ((rx_status & RX_STAT_CTL_OWNER_MSK) ==
(RXSF_HWDONE << RX_STAT_CTL_OWNER_SHF)) {
/* Check the rx status. */
if (rx_status & (RX_STATUS_GOOD << RX_STAT_CTL_STATUS_SHF)) {
/* Received packet is good. */
len = (rx_status & RX_STAT_CTL_LENGTH_MSK) >>
RX_STAT_CTL_LENGTH_SHF;
pData = (unsigned char *) pPacket;
pData += 4;
skb = dev_alloc_skb(len + 2);
if (skb == 0) {
printk
("%s: Memory squeeze, deferring packet.\n",
dev->name);
lp->stats.rx_dropped++;
} else {
lp->stats.rx_bytes += len;
lp->stats.rx_packets++;
skb->dev = dev;
skb_reserve(skb, 2); /* 16 byte align */
skb_put(skb, len); /* make room */
eth_copy_and_sum(skb,
(unsigned char *) pData,
len, 0);
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb);
}
} else {
/* We got an error packet. */
if (lan_saa9730_debug > 2)
static int lan_saa9730_cam_load(struct lan_saa9730_private *lp)
{
unsigned int i;
unsigned char *NetworkAddress;
NetworkAddress = (unsigned char *) &lp->PhysicalAddress[0][0];
for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) {
/* First set address to where data is written */
OUTL(i, &lp->lan_saa9730_regs->CamAddress);
OUTL((NetworkAddress[0] << 24) | (NetworkAddress[1] << 16)
| (NetworkAddress[2] << 8) | NetworkAddress[3],
&lp->lan_saa9730_regs->CamData);
NetworkAddress += 4;
}
return 0;
}
static int lan_saa9730_control_init(struct lan_saa9730_private *lp)
{
/* Initialize DMA control register. */
OUTL((LANMB_ANY << DMA_CTL_MAX_XFER_SHF) |
(LANEND_LITTLE << DMA_CTL_ENDIAN_SHF) |
(LAN_SAA9730_RCV_Q_INT_THRESHOLD << DMA_CTL_RX_INT_COUNT_SHF)
| DMA_CTL_RX_INT_TO_EN | DMA_CTL_RX_INT_EN |
DMA_CTL_MAC_RX_INT_EN | DMA_CTL_MAC_TX_INT_EN,
&lp->lan_saa9730_regs->LanDmaCtl);
/* Initial MAC control register. */
OUTL((MACCM_MII << MAC_CONTROL_CONN_SHF) | MAC_CONTROL_FULL_DUP,
&lp->lan_saa9730_regs->MacCtl);
/* Initialize CAM control register. */
OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC,
&lp->lan_saa9730_regs->CamCtl);
/*
* Initialize CAM enable register, only turn on first entry, should
* contain own addr.
*/
OUTL(0x0001, &lp->lan_saa9730_regs->CamEnable);
/* Initialize Tx control register */
OUTL(TX_CTL_EN_COMP, &lp->lan_saa9730_regs->TxCtl);
/* Initialize Rcv control register */
OUTL(RX_CTL_STRIP_CRC, &lp->lan_saa9730_regs->RxCtl);
/* Reset DMA engine */
OUTL(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest);
return 0;
}
void
bctv2_gpio_write( bktr_ptr_t bktr, int port, int val )
{
u_long data, outbits;
port &= BCTV2_GPIO_PORT_MASK;
switch (port) {
case 1:
case 3:
data = ((val << BCTV2_GPIO_VAL_SHIFT) & BCTV2_GPIO_VAL_MASK) |
((port << BCTV2_GPIO_ADDR_SHIFT) & BCTV2_GPIO_ADDR_MASK) |
BCTV2_GPIO_WE | BCTV2_GPIO_OE;
outbits = BCTV2_GPIO_OUT_WMASK;
break;
default:
return;
}
OUTL(bktr, BKTR_GPIO_OUT_EN, 0);
OUTL(bktr, BKTR_GPIO_DATA, data);
OUTL(bktr, BKTR_GPIO_OUT_EN, outbits);
DELAY(BCTV2_BITS);
OUTL(bktr, BKTR_GPIO_DATA, data & ~BCTV2_GPIO_WE);
DELAY(BCTV2_BITS);
OUTL(bktr, BKTR_GPIO_DATA, data);
DELAY(BCTV2_BITS);
OUTL(bktr, BKTR_GPIO_DATA, ~0);
OUTL(bktr, BKTR_GPIO_OUT_EN, 0);
}
/*
* Read PCI configuration register of device and return its content
*/
u_int32_t
pci_read_reg(struct pci_entry_t *c, u_int8_t reg) {
u_int32_t data;
data = PCI_CYCLE_ENABLE_BIT;
data |= PCI_BUS_NO(c->bus) | PCI_DEV_NO(c->dev) | PCI_FUN_NO(c->fun);
data |= PCI_REG_ADDR(reg);
OUTL(CONFIG_ADDRESS, data);
return inl(CONFIG_DATA);
}
static void
ns8382x_check_duplex(struct eth_device *dev)
{
int gig = 0;
int hun = 0;
int duplex = 0;
int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
duplex = (config & FullDuplex) ? 1 : 0;
gig = (config & GigSpeed) ? 1 : 0;
hun = (config & HundSpeed) ? 1 : 0;
#ifdef NS8382X_DEBUG
printf("%s: Setting 10%s %s-duplex based on negotiated link"
" capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
duplex ? "full" : "half");
#endif
if (duplex) {
rx_config |= RxAcceptTx;
tx_config |= (TxCarrierIgn | TxHeartIgn);
} else {
rx_config &= ~RxAcceptTx;
tx_config &= ~(TxCarrierIgn | TxHeartIgn);
}
#ifdef NS8382X_DEBUG
printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
#endif
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
/*if speed is 10 or 100, remove MODE1000,
* if it's 1000, then set it */
config = INL(dev, ChipConfig);
if (gig)
config |= Mode1000;
else
config &= ~Mode1000;
#ifdef NS8382X_DEBUG
printf("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
#endif
OUTL(dev, config, ChipConfig);
}
static int lan_saa9730_dma_init(struct lan_saa9730_private *lp)
{
/* Stop lan controller. */
lan_saa9730_stop(lp);
OUTL(LAN_SAA9730_DEFAULT_TIME_OUT_CNT,
&lp->lan_saa9730_regs->Timeout);
return 0;
}
static void
ns8382x_init_rxfilter(struct eth_device *dev)
{
int i;
for (i = 0; i < ETH_ALEN; i += 2) {
OUTL(dev, i, RxFilterAddr);
OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
RxFilterData);
}
}
void
atge_l1e_stop_mac(atge_t *atgep)
{
uint32_t reg;
reg = INL(atgep, ATGE_MAC_CFG);
ATGE_DB(("%s: %s() reg : %x", atgep->atge_name, __func__, reg));
if ((reg & (ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB)) != 0) {
reg &= ~ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB;
OUTL(atgep, ATGE_MAC_CFG, reg);
ATGE_DB(("%s: %s() mac stopped", atgep->atge_name, __func__));
}
}
static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
{
uint8_t val;
/* FIXME: Can we skip reading the old data and simply use 0? */
/* Read old data. */
val = INB(io_base_addr + bios_rom_data);
/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
io_base_addr + bios_rom_addr);
/* Read new data. */
val = INB(io_base_addr + bios_rom_data);
/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
io_base_addr + bios_rom_addr);
return val;
}
static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
const chipaddr addr)
{
OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
/*
* The datasheet requires 32 bit accesses to this register, but it seems
* that requirement might only apply if the register is memory mapped.
* Bits 8-31 of this register are apparently don't care, and if this
* register is I/O port mapped, 8 bit accesses to the lowest byte of the
* register seem to work fine. Due to that, we ignore the advice in the
* data sheet.
*/
return INB(io_base_addr + BOOT_ROM_DATA);
}
static void
mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
{
int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
int i;
/* Shift the command bits out. */
for (i = 31; i >= 0; i--) {
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
OUTL(dev, dataval, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
/* Clear out extra bits. */
for (i = 2; i > 0; i--) {
OUTL(dev, MDIO_EnbIn, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
return;
}
static void
ns8382x_set_rx_mode(struct eth_device *dev)
{
u32 rx_mode = 0x0;
/*spec says RxFilterEnable has to be 0 for rest of
* this stuff to be properly configured. Linux driver
* seems to support this*/
/* OUTL(dev, rx_mode, RxFilterAddr);*/
rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
OUTL(dev, rx_mode, RxFilterAddr);
printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
/*now we turn RxFilterEnable back on */
/*rx_mode |= RxFilterEnable;
OUTL(dev, rx_mode, RxFilterAddr);*/
}
static int
ac97_read (void *devc_, int index)
{
oss_native_word access;
unsigned int data;
unsigned i, N;
unsigned char byte;
oss_native_word flags;
als300_devc *devc = devc_;
MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
i = 0;
N = 1000;
do
{
byte = INB (devc->osdev, devc->base + 6) & 0x80;
if (byte == 0x00)
goto next;
oss_udelay (10);
i++;
}
while (i < N);
if (i >= N)
cmn_err (CE_WARN, "\n Write AC97 mixer index time out !!");
next:
access = index;
access <<= 24; /*index */
access |= 0x80000000;
OUTL (devc->osdev, access, devc->base);
i = 0;
N = 1000;
do
{
byte = INB (devc->osdev, devc->base + 6);
if ((byte & 0x40) != 0)
goto next1;
oss_udelay (10);
i++;
}
while (i < N);
if (i >= N)
cmn_err (CE_WARN, "Read AC97 mixer data time out !!");
next1:
data = INW (devc->osdev, devc->base + 0x04);
MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
return data;
}
void
usage()
{
OUTL("packetgen [-# seedX] [-% seedY] [-I] [-a ipAddr] [-p port] [-x] [-y] [-f packetFilename]\n"
" [-c channel] [-s source] [-C ] [-b] [-l]\n "
" [-n numberOfPackets] [-i wakeupInterval]\n "
" [-P noise power] [-B bandwidth]\n "
" [-U usable fraction of bandwidth]\n "
" [-X signal in X pol only]\n"
" [-Y signal in Y pol only]\n"
" [-Z signal in both pols]\n"
" [-O pulse time ON]\n"
" [-o pulse time OFF]\n"
" [-R Center Frequency]\n"
" {[-S snr] [-D drift] [-F freq]}");
exit(-1);
}
void
atge_l1e_send_packet(atge_ring_t *r, int start, uint32_t pktlen)
{
atge_l1e_tx_desc_t *txd;
uchar_t *c;
uint32_t cflags = 0;
c = (uchar_t *)r->r_desc_ring->addr;
c += (sizeof (atge_l1e_tx_desc_t) * start);
txd = (atge_l1e_tx_desc_t *)c;
ATGE_PUT64(r->r_desc_ring, &txd->addr,
r->r_buf_tbl[start]->cookie.dmac_laddress);
ATGE_PUT32(r->r_desc_ring, &txd->len, L1E_TX_BYTES(pktlen));
cflags |= L1E_TD_EOP;
ATGE_PUT32(r->r_desc_ring, &txd->flags, cflags);
/*
* Sync buffer first.
*/
DMA_SYNC(r->r_buf_tbl[start], 0, pktlen, DDI_DMA_SYNC_FORDEV);
/*
* Increment TX producer count by one.
*/
ATGE_DESC_INC(r->r_producer, L1E_TX_RING_CNT);
/*
* Sync descriptor table.
*/
DMA_SYNC(r->r_desc_ring, 0, L1E_TX_RING_SZ, DDI_DMA_SYNC_FORDEV);
/*
* Ask chip to send the packet now.
*/
OUTL(r->r_atge, ATGE_MBOX, r->r_producer);
r->r_atge->atge_opackets++;
r->r_atge->atge_obytes += pktlen;
}
