_WMRTLINK complex _IF_C8Div( single a, single b, single c, single d ) {
//====================================================================
// Divide two complex numbers and return the real part of the result.
// ( a, b )/( c, d ) = (( a, b )/( d + c*c/d )) * ( c/d, -1 )
single tmp;
single quo;
complex res;
if( fabs( d ) < fabs( c ) ) {
tmp = a; // convert to (-b,a)/(-d,c)
a = - b;
b = tmp;
tmp = c;
c = -d;
d = tmp;
}
quo = PDIV( c , d );
tmp = quo * c + d;
a = PDIV( a, tmp );
b = PDIV( b, tmp );
c = quo;
res.realpart = a * c + b;
res.imagpart = b * c - a;
return( res );
}
_WMRTLINK extended _IF_PowXI( extended base, intstar4 power ) {
//============================================================
// Return base ** power where power could be <= 0.
extended result;
if( base == 0.0 ) {
if( power <= 0 ) {
result = power;
return( __math2err( FUNC_DPOWI | M_DOMAIN | V_ZERO, &base, &result ) );
} else {
return( 0.0 );
}
} else {
if( power < 0 ) {
power = -power;
base = PDIV( 1.0 , base );
}
result = 1.0;
while( power > 0 ) {
if( power % 2 == 0 ) {
base *= base;
power /= 2;
} else {
result *= base;
--power;
}
}
return( result );
}
}
void __s5p_tv_clk_init_hpll(unsigned int lock_time,
bool vsel,
unsigned int mdiv,
unsigned int pdiv,
unsigned int sdiv)
{
u32 temp;
TVCLKPRINTK("%d,%d,%d,%d\n\r", lock_time, mdiv, pdiv, sdiv);
temp = readl(S5P_VPLL_CON);
temp &= ~VPLL_ENABLE;
writel(temp, S5P_VPLL_CON);
temp = 0;
if(vsel)
temp |= VCO_FREQ_SEL;
temp |= VPLL_ENABLE;
temp |= MDIV(mdiv) | PDIV(pdiv) | SDIV(sdiv);
writel(VPLL_LOCKTIME(lock_time), S5P_VPLL_LOCK);
writel(temp, S5P_VPLL_CON);
while(!VPLL_LOCKED(readl(S5P_VPLL_CON)));
TVCLKPRINTK("0x%08x,0x%08x\n\r", readl(S5P_VPLL_LOCK), readl(S5P_VPLL_CON));
}
_WMRTLINK double _IF_dsinh( double x )
/************************************/
{
unsigned int err_code;
double z;
z = fabs( x );
if( z > 709.782712893384 ) { /* if argument is too large */
if( x < 0.0 ) {
err_code = FP_FUNC_SINH | M_OVERFLOW | V_NEG_HUGEVAL;
} else {
err_code = FP_FUNC_SINH | M_OVERFLOW | V_HUGEVAL;
}
z = __math1err( err_code, &x );
} else {
/* if( z <= ldexp( 1.0, -26 ) ) { */
if( z <= 1.49011611938476580e-008 ) { /* if x is small */
z = x;
} else {
z = exp( x );
z = (z - PDIV( 1.0, z )) / 2.0;
}
}
return( z );
}
_WMRTLINK double _IF_datan( double x )
/************************************/
{
char add_piby2;
char add_piby6;
int sgnx;
double tmp;
#if defined(_M_IX86)
if( _RWD_real87 )
return( _atan87(x) );
#endif
add_piby2 = FALSE;
add_piby6 = FALSE;
sgnx = __sgn( x );
x = fabs( x );
if( x == 1.0 ) { /* 06-dec-88 */
x = PIby4;
} else if( x > (1.0 / DBL_MIN) ) {
x = PIby2;
} else if( x < (DBL_MIN / MIN_POLY_CONST) ) {
x = DBL_MIN;
} else {
if( x > 1.0 ) {
x = PDIV( 1.0, x );
add_piby2 = TRUE;
}
if( x > tan15 ) {
tmp = sqrt3m1 * x - 0.5;
tmp -= 0.5;
x = PDIV( (tmp + x), (x + sqrt3) );
// x = (x * sqrt3 - 1.0) / (x + sqrt3);
add_piby6 = TRUE;
}
x = _OddPoly( x, AtanPoly, 8 );
if( add_piby6 ) {
x += PIby6;
}
if( add_piby2 ) {
x = PIby2 - x;
}
}
if( sgnx < 0 ) {
x = -x;
}
return( x );
}
void __s5p_tv_clk_init_hpll(unsigned int lock_time,
unsigned int mdiv,
unsigned int pdiv,
unsigned int sdiv)
{
TVCLKPRINTK("%d,%d,%d,%d\n\r", lock_time, mdiv, pdiv, sdiv);
writel(HPLL_LOCKTIME(lock_time), S5P_HPLL_LOCK);
writel(MDIV(mdiv) | PDIV(pdiv) | SDIV(sdiv), S5P_HPLL_CON);
TVCLKPRINTK("0x%08x,0x%08x\n\r", readl(S5P_HPLL_LOCK),
readl(S5P_HPLL_CON));
}
_WMRTLINK double j1( double x ) /* Bessel function j1(x) */
/*****************************/
{
double ax, xx, y, z;
ax = fabs( x );
if( ax < 8.0 ) {
y = x * x;
z = PDIV( x * _EvalPoly( y, _J1P, 7 ) , _EvalPoly( y, _J1Q, 7 ) );
} else {
z = PDIV( 8.0, ax );
y = z * z;
xx = ax - ThreePIby4;
z = sqrt( PDIV( TwobyPI, ax ) ) *
( PDIV( cos( xx ) * _EvalPoly( y, _P1P, 4 ) , _EvalPoly( y, _P1Q, 5 ) )
- z * sin( xx ) * (PDIV( _EvalPoly( y, _Q1P, 4 ) , _EvalPoly( y, _Q1Q, 4 ) )) );
if( x < 0.0 ) {
z = - z;
}
}
return( z );
}
static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int vpll_con;
switch (rate) {
case 54000000:
vpll_con = PDIV(6) | MDIV(108) | SDIV(3);
break;
case 27000000:
vpll_con = PDIV(6) | MDIV(108) | SDIV(4);
break;
default:
goto err_on_invalid_rate;
}
__raw_writel(vpll_con, S5P_VPLL_CON);
clk->rate = rate;
return 0;
err_on_invalid_rate:
return -EINVAL;
}
_WMRTLINK double _IF_dcosh( double x )
/*************************/
{
double z;
z = fabs( x );
if( z > 709.782712893384 ) { /* if argument is too large */
// z = _matherr( OVERFLOW, "cosh", &x, &x, HUGE_VAL );
z = __math1err( FUNC_COSH | M_OVERFLOW | V_HUGEVAL, &x );
} else {
/* if( z <= ldexp( 1.0, -26 ) ) { */
if( z <= 1.49011611938476580e-008 ) { /* if x is small */
z = 1.0;
} else {
z = exp( x );
z = (z + PDIV( 1.0 , z) ) / 2.0;
}
}
return( z );
}
_WMRTLINK double yn( int n, double x )
/**************************/
{
int j;
double by, bym, byp, tox;
if( x < 0.0 ) {
return __math1err( FP_FUNC_YN | M_DOMAIN | V_NEG_HUGEVAL, &x );
}
bym = y0( x );
if( n == 0 )
return( bym );
tox = PDIV( 2.0, x );
by = y1( x );
for( j = 1; j < n; j++ ) {
byp = j * tox * by - bym;
bym = by;
by = byp;
}
return( by );
}
_WMRTLINK double _IF_dtanh( double x )
/************************************/
{
double z;
z = fabs( x );
if( z >= 64.0 ) {
if( x < 0.0 ) {
z = -1.0;
} else {
z = 1.0;
}
} else {
/* if( z <= ldexp( 1.0, -26 ) ) { */
if( z <= 1.49011611938476580e-008 ) { /* if x is small */
z = x;
} else {
z = exp( (-2.0) * x );
z = PDIV( (1.0 - z), (1.0 + z) );
}
}
return( z );
}
_WMRTLINK double y1( double x ) /* Bessel function y1(x) */
/*******************/
{
double xx, y, z;
if( x < 0.0 ) {
// z = _matherr( DOMAIN, "y1", &x, &x, - HUGE_VAL );
z = __math1err( FUNC_Y1 | M_DOMAIN | V_NEG_HUGEVAL, &x );
} else if( x < 8.0 ) {
y = x * x;
z = PDIV( x * _EvalPoly( y, _Y1P, 10 ) , _EvalPoly( y, _Y1Q, 4 ) )
+ Two_over_pi * ( j1(x) * log(x) - PDIV(1.0,x) );
} else {
z = PDIV( 8.0 , x );
y = z * z;
xx = x - ThreePIby4;
z = sqrt( PDIV( Two_over_pi , x ) ) *
( PDIV( sin(xx) * _EvalPoly( y, _P1P, 4 ) , _EvalPoly( y, _P1Q, 5 ) )
+ z * cos(xx) *(PDIV(_EvalPoly( y, _Q1P, 4 ) , _EvalPoly( y, _Q1Q, 4 ))));
}
return( z );
}
static void board_clock_init(void)
{
unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
samsung_get_base_clock();
/*
* CMU_CPU clocks src to MPLL
* Bit values: 0 ; 1
* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
*/
clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
MUX_MPLL_USER_SEL_C(1);
clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
continue;
/* Set APLL to 1000MHz */
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;
/* Set CMU_CPU clocks src to APLL */
set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
MUX_MPLL_USER_SEL_C(1);
clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
continue;
set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
APLL_RATIO(0) | CORE2_RATIO(0);
/*
* Set dividers for MOUTcore = 1000 MHz
* coreout = MOUT / (ratio + 1) = 1000 MHz (0)
* corem0 = armclk / (ratio + 1) = 333 MHz (2)
* corem1 = armclk / (ratio + 1) = 166 MHz (5)
* periph = armclk / (ratio + 1) = 1000 MHz (0)
* atbout = MOUT / (ratio + 1) = 200 MHz (4)
* pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
* sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
* core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
*/
clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
APLL_RATIO(7) | CORE2_RATIO(7);
clrsetbits_le32(&clk->div_cpu0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;
/*
* For MOUThpm = 1000 MHz (MOUTapll)
* doutcopy = MOUThpm / (ratio + 1) = 200 (4)
* sclkhpm = doutcopy / (ratio + 1) = 200 (4)
* cores_out = armclk / (ratio + 1) = 200 (4)
*/
clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
clrsetbits_le32(&clk->div_cpu1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
continue;
/*
* Set CMU_DMC clocks src to APLL
* Bit values: 0 ; 1
* MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
* MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
* MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
* MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
* MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
* MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
* MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
* MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
*/
clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
continue;
/* Set MPLL to 800MHz */
set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
/* Wait for PLL to be locked */
while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;
/* Switch back CMU_DMC mux */
set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
/* Wait for mux change */
while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
continue;
/* CLK_DIV_DMC0 */
clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
/*
* For:
* MOUTdmc = 800 MHz
* MOUTdphy = 800 MHz
*
* aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
* pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
* sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
* sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
* aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
* aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
*/
set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
clrsetbits_le32(&clk->div_dmc0, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
continue;
/* CLK_DIV_DMC1 */
clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
/*
* For:
* MOUTg2d = 800 MHz
* MOUTc2c = 800 Mhz
* MOUTpwi = 108 MHz
*
* sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
* sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
* aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
* sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
*/
set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
clrsetbits_le32(&clk->div_dmc1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
continue;
/* CLK_SRC_PERIL0 */
clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
UART3_SEL(15) | UART4_SEL(15);
/*
* Set CLK_SRC_PERIL0 clocks src to MPLL
* src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
* 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
* 8(SCLK_VPLL)
*
* Set all to SCLK_MPLL_USER_T
*/
set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
UART4_SEL(6);
clrsetbits_le32(&clk->src_peril0, clr, set);
/* CLK_DIV_PERIL0 */
clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15) | UART4_RATIO(15);
/*
* For MOUTuart0-4: 800MHz
*
* SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
*/
set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
UART3_RATIO(7) | UART4_RATIO(7);
clrsetbits_le32(&clk->div_peril0, clr, set);
while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
continue;
/* CLK_DIV_FSYS1 */
clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
MMC1_PRE_RATIO(255);
/*
* For MOUTmmc0-3 = 800 MHz (MPLL)
*
* DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
* sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
* DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
* sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
*/
set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
MMC1_PRE_RATIO(1);
clrsetbits_le32(&clk->div_fsys1, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;
/* CLK_DIV_FSYS2 */
clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
MMC3_PRE_RATIO(255);
/*
* For MOUTmmc0-3 = 800 MHz (MPLL)
*
* DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
* sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
* DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
* sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
*/
set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
MMC3_PRE_RATIO(1);
clrsetbits_le32(&clk->div_fsys2, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
continue;
/* CLK_DIV_FSYS3 */
clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
/*
* For MOUTmmc4 = 800 MHz (MPLL)
*
* DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
* sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
*/
set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
clrsetbits_le32(&clk->div_fsys3, clr, set);
/* Wait for divider ready status */
while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
continue;
return;
}
_WMRTLINK double _IF_datan2( double y, double x )
/***********************************************/
{
int sgnx; /* sgn(x) */
int sgny; /* sgn(y) */
int sgnz; /* sgn(z) */
sgny = __sgn( y );
sgnx = __sgn( x );
if( sgny == 0 ) { /* case 1 */
if( sgnx == 0 ) {
x = __math2err( FUNC_ATAN2 | M_DOMAIN | V_ZERO, &y, &x );
} else if( sgnx < 0 ) {
x = Pi;
} else {
x = 0.0;
}
} else if( sgnx == 0 ) { /* case 2 */
if( sgny < 0 ) {
x = -Piby2;
} else {
x = Piby2;
}
} else {
int exp_x;
int exp_y;
int diff_exp_y_x;
frexp( y, &exp_y );
frexp( x, &exp_x );
diff_exp_y_x = exp_y - exp_x;
if( diff_exp_y_x > DBL_MAX_EXP ) {
if( sgnx == sgny ) {
x = +DBL_MAX;
} else {
x = -DBL_MAX;
}
} else if( diff_exp_y_x < DBL_MIN_EXP ) {
if( sgnx == sgny ) {
x = +DBL_MIN;
} else {
x = -DBL_MIN;
}
} else {
x = PDIV( y, x );
}
x = atan( x );
sgnz = __sgn( x );
if( sgny >= 0 ) {
if( sgnz < 0 ) {
x += Pi;
}
} else {
if( sgnz > 0 ) {
x -= Pi;
}
}
}
return( x );
}
