/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_busmon_clock()
{
    /*
     * The clock should be available before the AXI transaction issued
     * Designer does not recommended to turn on clock at the run time
     */
#if defined(__SS_SPV_LOAD__)&&defined(__SWLA_ADDON_BMON__)

  #if defined(MT6290)
    PDN_CLR(PDN_APPERI_BUSMON);
  #else  /* Chip dependent */
    PDN_CLR(PDN_MDINFRA_BUSMON);
  #endif /* Chip dependent */

#else  /* __SS_SPV_LOAD__ && __SWLA_ADDON_BMON__*/

    PDN_SET(PDN_MDMCU_BUSMON);
    PDN_SET(PDN_MDINFRA_BUSMON);

  #if defined(MT6290)
    PDN_SET(PDN_APPERI_BUSMON);
    PDN_SET(PDN_APMCU_BUSMON);
  #endif

#endif /* __SS_SPV_LOAD__ && __SWLA_ADDON_BMON__ */
}
Exemplo n.º 2
0
void adc_pwrdown_enable(void)
{
#ifndef DRV_ADC_NOT_EXIST
#ifndef DRV_ADC_NO_PDN

   #if (!defined(DRV_ADC_6208_PWRDOWN)) && (!defined(DRV_ADC_MODEM_SIDE))
   if((adc_sche_rw_status==0)&&!(DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN))
   #endif // #if (!defined(DRV_ADC_6208_PWRDOWN)) && (!defined(DRV_ADC_MODEM_SIDE))
   {
      #if defined(__OLD_PDN_ARCH__)
      #ifdef ADC_DRVPDN_FAST
      DRVPDN_ENABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
      #else /*ADC_DRVPDN_FAST*/
      DRVPDN_Enable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
      #endif /*ADC_DRVPDN_FAST*/
      #else // #if defined(__OLD_PDN_ARCH__)
      #ifdef ADC_DRVPDN_FAST
      DRVPDN_ENABLE2(PDN_ADC);
      #else /*ADC_DRVPDN_FAST*/
      //DRVPDN_Enable(PDN_ADC);

	PDN_SET(PDN_ADC);
	L1SM_SleepEnable(ADCSM_handler);   
	  
      #endif /*ADC_DRVPDN_FAST*/
      #endif // #if defined(__OLD_PDN_ARCH__)
   }

#endif //#ifndef DRV_ADC_NO_PDN
#endif // #ifndef DRV_ADC_NOT_EXIST

}
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_sdio_clock()
{
#ifdef MT6290
 #if !defined(__X_BOOTING__)
    
    *SDIO_CTRL_HGFCR |= SDIO_PAD_CR_SET_BY_FW;

    *SDIO_PAD_FWCLKIOCR |= SDIO_PAD_CLK_PUPD;
    *SDIO_PAD_FWCMDIOCR |= SDIO_PAD_CLK_PUPD;
    *SDIO_PAD_FWDAT0IOCR |= SDIO_PAD_CLK_PUPD;
    *SDIO_PAD_FWDAT1IOCR |= SDIO_PAD_CLK_PUPD;
    *SDIO_PAD_FWDAT2IOCR |= SDIO_PAD_CLK_PUPD;
    *SDIO_PAD_FWDAT3IOCR |= SDIO_PAD_CLK_PUPD;


    *SDIO_PAD_FWCLKIOCR |= ORG_SDIO_PAD_50K_RESISTOR;
    *SDIO_PAD_FWCMDIOCR |= ORG_SDIO_PAD_50K_RESISTOR;
    *SDIO_PAD_FWDAT0IOCR |= ORG_SDIO_PAD_50K_RESISTOR;
    *SDIO_PAD_FWDAT1IOCR |= ORG_SDIO_PAD_50K_RESISTOR;
    *SDIO_PAD_FWDAT2IOCR |= ORG_SDIO_PAD_50K_RESISTOR;
    *SDIO_PAD_FWDAT3IOCR |= ORG_SDIO_PAD_50K_RESISTOR;
 
    PDN_SET(PDN_SDIO);
 
 #endif
#endif /* MT6290 */
}
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_ehpi_slave_clock()
{
    #if defined(MT6290)
    // Gating eHPI-slave bus clock (source clock is from AHB)
    PDN_SET(PDN_EHPI_SLAVE);
    #else//#if defined(MT6290)
    #endif//#if defined(MT6290)
}
Exemplo n.º 5
0
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_msdc_clock()
{
    /* Router project */
    #if defined(__SMART_PHONE_MODEM__) && !defined(__X_BOOTING__)
        /* 
         * Do nothing, because the ownership is at AP side,
         * and it assumes that the APMCU would handle the AP's CLKCTL
         */
        
    /* Phone project */
    #elif defined(__SMART_PHONE_MODEM__) && defined(__X_BOOTING__)
        /* 
         * In phone project, both MSDC0&1 should be shut down
         */
        PDN_SET(PDN_MSDC0);
        PDN_SET(PDN_MSDC1);
        IPCG_SET(IPCG_MSDC0);
        IPCG_SET(IPCG_MSDC1);

    /* Host dongle project */
    #elif defined(__MODEM_CARD__) && !defined(__TRADITIONAL_MODEM_CARD__)
        /* 
         * In dongle project, MSDC0 would be run-time PDN_SET/PDN_CLR 
         * by MSDC0 driver
         */
        PDN_SET(PDN_MSDC1);
        IPCG_SET(IPCG_MSDC1);

    /* Traditional dongle project */        
    #elif defined(__MODEM_CARD__) && defined(__TRADITIONAL_MODEM_CARD__)
        /* 
         * In dongle project, MSDC0 would be run-time PDN_SET/PDN_CLR 
         * by MSDC0 driver
         */
        PDN_SET(PDN_MSDC1);
        IPCG_SET(IPCG_MSDC1);
    #endif
}
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_nic_clock()
{
#if defined(MT6290)
#if defined(__SMART_PHONE_MODEM__) && !defined(__X_BOOTING__)      //router
	    //NIC in router product will be controlled by AP
#elif defined(__MODEM_CARD__) && !(defined(__TRADITIONAL_MODEM_CARD__))        //hosted dongle

#else

	//NIC will not be used on phone/traditional dongle, so power down it directly
	IPCG_SET(IPCG_NIC);
	PDN_SET(PDN_NIC);
#endif
#endif
}
Exemplo n.º 7
0
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_ehpi_master_clock()
{
    #if defined(MT6290)
    /* Router project */
    #if defined(__SMART_PHONE_MODEM__) && !(defined(__X_BOOTING__))
    /* 
     * Do nothing, because the ownership is at AP side,
     * and it assumes that the APMCU would handle the AP's CLKCTL
     */
    #else
    PDN_SET(PDN_EHPI_MASTER);// bus clock off
    #endif//end of #if defined(__SMART_PHONE_MODEM__) && !(defined(__X_BOOTING__))
    #else//#if defined(MT6290)
    
    #endif//#if defined(MT6290)
}
/*
* FUNCTION                                                            
*	UPLL_Disable
*
* DESCRIPTION                                                           
*   	This function is to disable UPLL
*
* CALLS  
*	It is called to disable UPLL
*
* PARAMETERS
*	owner = UPLL owner
*	
* RETURNS
*	None
*
* GLOBALS AFFECTED
*   external_global
*/
void UPLL_Disable(UPLL_OWNER owner)
{
#if  (defined(DRV_UPLL_V1)||defined(DRV_UPLL_V2)||defined(DRV_UPLL_V3)||defined(DRV_UPLL_V4)||defined(DRV_UPLL_V5)||defined(DRV_UPLL_V6)||defined(DRV_UPLL_V7)||defined(DRV_UPLL_V8)|| defined(DRV_USB_UPLL_MT50_SERIES))

	kal_uint32 savedMask;
   
	if(owner >= UPLL_OWNER_MAX)
		EXT_ASSERT(0, (kal_uint32)owner, g_upll_owner, 0);

	savedMask = SaveAndSetIRQMask();   
	g_upll_owner &= ~(1<<(kal_uint32)owner);
	if(g_upll_owner == 0)
	{
#if defined(DRV_UPLL_V1)
		USB_DRV_SetBits(DRVPDN_CON0_SET , DRVPDN_CON0_UPLL);	
#elif defined(DRV_UPLL_V2)
		/* hardware issue */
		USB_PDNEnable(USB_PDN_OWNER_UPLL);
		USB_DRV_SetBits(DRVPDN_CON0_SET , DRVPDN_CON0_UPLL);	
#elif defined(DRV_UPLL_V3)
		/* select UPLL clock source bypassed PLL  */
		USB_DRV_ClearBits(PLL , 0x0040);
#elif defined(DRV_UPLL_V4)
//		DRV_Reg(DRVPDN_CON0) |= (DRVPDN_CON0_PLL2);
#elif defined(DRV_UPLL_V5)

#elif defined(DRV_UPLL_V6)
//    DRV_Reg(PDN_CON)&= ~(0x0010);  // set this bit will also clear MPLL
#elif defined(DRV_UPLL_V7)
//    DRV_Reg(UPLL_CON1)&= ~(0x0002);
#elif defined(DRV_UPLL_V8)
	USB_DRV_ClearBits(GPLL_CON0, 0x0080);
#elif defined(DRV_USB_UPLL_MT50_SERIES)
	if (SW_SEC_0 == INT_SW_SecVersion()) 
	{
		PDN_SET(PDN_USB_48M);
	}		
#endif
	}
	RestoreIRQMask(savedMask);
#endif

}
Exemplo n.º 9
0
void adc_pwrdown_enable(void)
{
#ifndef DRV_ADC_NOT_EXIST
   {
	  #if defined(DRV_DIE_TO_DIE_INTERFACE)
	  {
	  	   kal_uint32 mask;
		   
		   mask = SaveAndSetIRQMask();
		   auxadc_die2die_enable = KAL_FALSE;  
		 
		   DRV_ADC_ClearBits(ABB_AUX_CON0, AUX_FIFO_EN);  // auxadc fifo enable
		   DRV_ADC_ClearBits(ABB_AUX_CON0, AUX_FIFO_CLK_EN);	// auxadc fifo enable

	  	   ust_busy_wait(8);	
		   
		   DRV_ADC_ClearBits(ABB_WR_PATH0, AUX_PWDB);			//triggle die to die interface to send and receive auxadc data
		   DRV_ADC_ClearBits(ABBA_WR_PATH0, ABBA_AUX_PWDB);		// enable clock for auxadc analog interface logic

		//   DRV_ADC_ClearBits(ABB_WR_PATH0, F26M_CLK_EN);		//enable clock for die to die interface
		//   DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_FSM_CTRL|AUXADC_26M_CLK_CTRL);		//enable clock for die to die interface

	       DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_FSM_CTRL);		//enable clock for die to die interface
		   ust_busy_wait(2);	
		   DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_26M_CLK_CTRL);		//enable clock for die to die interface

		   PDN_SET(PDN_ADC);	// TP use the AuxADC PDN, make sure the PDN is enable
		   
		   	DRV_ADC_ClearBits(0xa0160020,0x8000);
		   RestoreIRQMask(mask);
	  } 
	  #elif defined(DRV_DIE_TO_DIE_INTERFACE_V2)
	  {

		   DRV_ADC_ClearBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN);
		   DRV_ADC_ClearBits(D2D_A_APC_AUD_CON1, D2D_A_AUX_EN);
		   ust_busy_wait(8);
		   DRV_ADC_ClearBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN | D2D_D_F26M_AUX_EN);
	  }
         #endif		 

	   
	  
      #if defined(__OLD_PDN_ARCH__)
      #ifdef ADC_DRVPDN_FAST
      DRVPDN_ENABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
      #else /*ADC_DRVPDN_FAST*/
      DRVPDN_Enable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
      #endif /*ADC_DRVPDN_FAST*/
      #else // #if defined(__OLD_PDN_ARCH__)
      #ifdef ADC_DRVPDN_FAST
      DRVPDN_ENABLE2(PDN_ADC);
      #else /*ADC_DRVPDN_FAST*/

#if !defined(__DRV_SUPPORT_LPWR__)
	PDN_SET(PDN_ADC);
	L1SM_SleepEnable(ADCSM_handler);   
#else
        DRVPDN_Enable(PDN_ADC);
#endif //#if !defined(__DRV_SUPPORT_LPWR__)	  
	  
      #endif /*ADC_DRVPDN_FAST*/
      #endif // #if defined(__OLD_PDN_ARCH__)
   }

#endif // #ifndef DRV_ADC_NOT_EXIST

}
/*-----------------------------------------------------------------------*
*                                                          
*  This function is to close GPT source clock.
*
*------------------------------------------------------------------------*/
static void GPT_PDN_disable()
{
	#if !defined(DRV_GPT_NO_PDN_BIT)
#if defined(__OLD_PDN_ARCH__)
#if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
	// Set GPT PDN bit directly
	#if defined(DRV_MISC_PDN_NO_SET_CLR)
#if defined(__OLD_PDN_DEFINE__)
		DRV_GPT_SetBits(DRVPDN_CON1, DRVPDN_CON1_GPT);
		//DRV_GPT_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT;
#elif defined(__CLKG_DEFINE__)
		#if defined(DRV_GPT_NO_GPT_CG_BIT)
		;
		#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
		ASSERT(0);
		#endif // #if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
	#else // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#if defined(__OLD_PDN_DEFINE__)
		DRV_GPT_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT);
#elif defined(__CLKG_DEFINE__)
		#if defined(DRV_GPT_NO_GPT_CG_BIT)
		;
		#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
		ASSERT(0);
		#endif // #if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
	#endif // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#else // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
	// We need to to un-hook sleep mode handler to allow MCU enter sleep mode
#if defined(__OLD_PDN_DEFINE__)
#if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE)
	// Set GPT PDN bit directly
	#if defined(DRV_MISC_PDN_NO_SET_CLR)
		DRV_GPT_SetBits(DRVPDN_CON1, DRVPDN_CON1_GPT);
		//DRV_GPT_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT;
	#else // #if defined(DRV_MISC_PDN_NO_SET_CLR)
		DRV_GPT_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT);
	#endif // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#else // #if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE)
   #ifdef GPT_DRVPDN_FAST
	   DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);	   
   #else
	   DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);	  
   #endif
#endif
#elif defined(__CLKG_DEFINE__)
	#if defined(DRV_GPT_NO_GPT_CG_BIT)
	#ifdef GPT_DRVPDN_FAST
//	   DRVPDN_ENABLE2(0,0,PDN_GPT);  // TTTTTTTT, Temp commented for MT6268A DVT load	   
	#else // #ifdef GPT_DRVPDN_FAST
	   DRVPDN_Enable(0,0,PDN_GPT);	  
	#endif // #ifdef GPT_DRVPDN_FAST
	#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
		ASSERT(0);
	#endif // 	#if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
#endif // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
#else //#if defined(__OLD_PDN_ARCH__)
      PDN_SET(PDN_GPT);
#endif //#if defined(__OLD_PDN_ARCH__)
#endif //#if !defined(DRV_GPT_NO_PDN_BIT)
}
Exemplo n.º 11
0
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_nfi_clock()
{
#if defined(MT6290)
    PDN_SET(PDN_NFI);
#endif
}
Exemplo n.º 12
0
/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_i2c_clock()
{
#if defined(MT6290)
	PDN_SET(PDN_I2C);
#endif
}