void SYS_CLK_Initialize( const SYS_CLK_INIT const * clkInit )
{
SYS_DEVCON_SystemUnlock ( );
PLIB_OSC_FRCDivisorSelect( OSC_ID_0, OSC_FRC_DIV_2);
/* Enable Peripheral Bus 1 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 0, 1 );
/* Disable REFCLKO1*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, 0 );
/* Disable REFCLK1_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, 0 );
/* Disable REFCLKO2*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, 1 );
/* Disable REFCLK2_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, 1 );
/* Disable REFCLKO3*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, 2 );
/* Disable REFCLK3_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, 2 );
/* Disable REFCLKO4*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, 3 );
/* Disable REFCLK4_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, 3 );
SYS_DEVCON_SystemLock ( );
}
void SYS_CLK_Initialize( const SYS_CLK_INIT const * clkInit )
{
SYS_DEVCON_SystemUnlock ( );
PLIB_OSC_FRCDivisorSelect( OSC_ID_0, OSC_FRC_DIV_1);
/* Enable Peripheral Bus 1 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 0, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 0 );
/* Enable Peripheral Bus 2 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 1, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 1 );
/* Enable Peripheral Bus 3 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 2, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 2 );
/* Enable Peripheral Bus 4 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 3, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 3 );
/* Enable Peripheral Bus 5 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 4, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 4 );
/* Enable Peripheral Bus 7 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 6, 1 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 6 );
/* Enable Peripheral Bus 8 */
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, 7, 2 );
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, 7 );
/* Disable REFCLKO1*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, OSC_REFERENCE_1 );
/* Disable REFCLK1_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, OSC_REFERENCE_1 );
/* Disable REFCLKO2*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, OSC_REFERENCE_2 );
/* Disable REFCLK2_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, OSC_REFERENCE_2 );
/* Disable REFCLKO3*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, OSC_REFERENCE_3 );
/* Disable REFCLK3_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, OSC_REFERENCE_3 );
/* Disable REFCLKO4*/
PLIB_OSC_ReferenceOscDisable ( OSC_ID_0, OSC_REFERENCE_4 );
/* Disable REFCLK4_OE*/
PLIB_OSC_ReferenceOutputDisable ( OSC_ID_0, OSC_REFERENCE_4 );
SYS_DEVCON_SystemLock ( );
}
int8_t SYS_CLK_SystemClockSourceSwitch ( CLK_SOURCES_SYSTEM clockSource,
unsigned char valueToPLLMULT,
unsigned char valueToPLLODIV,
bool waitUntilComplete )
{
uint32_t delay= 100;
/* Unlock before you switch */
SYS_DEVCON_SystemUnlock ( );
/* Special treatment if the source is a PLL based source. Do not change
multipliers after switching. Switch to a FRC source first, then alter
the multiplier values. */
if ( ( ( clockSource == SYS_CLK_SOURCE_PRIMARY_SYSPLL ) ) ||
( clockSource == SYS_CLK_SOURCE_FRC_SYSPLL ) )
{
PLIB_OSC_SysClockSelect ( OSC_PLIB_ID, SYS_CLK_SOURCE_FRC );
/* Ensure that we are not on a PLL based source before switching */
/* Write the values before switching. Datasheet says so. */
PLIB_OSC_SysPLLMultiplierSelect ( OSC_PLIB_ID, valueToPLLMULT );
PLIB_OSC_SysPLLOutputDivisorSet ( OSC_PLIB_ID, valueToPLLODIV );
/* Switch to a PLL source */
PLIB_OSC_SysClockSelect ( OSC_PLIB_ID, clockSource );
delay = SYS_CLK_SYSPLL_LOCK_DELAY_80MHZ;
/* Wait till the PLL settles down / locked */
clkObject.systemClockStatus = SYS_CLK_OPERATION_IN_PROGRESS;
/* Device expects this delay. We are changing the System clock source here,
On debugging sometimes the code just stops without this delay. Have to
understand this further and fine tune this delay. */
Nop();
Nop();
Nop();
if ( waitUntilComplete == true )
{
//while ( PLIB_OSC_PLLIsLocked ( OSC_PLIB_ID, OSC_PLL_SYSTEM ) != true )
{
if ( delay-- <= 0 )
{
/* Rarest case. Either the PLL lock failed or the bit is showing
the wrong status, A restart needed, an error status update will
not help */
clkObject.systemClockStatus = SYS_CLK_OPERATION_FAIL_PLL_LOCK_TIMEOUT;
//SYS_ASSERT("PLL lock timeout");
Nop();
/* Reaching here means clock switching is not enabled
through configuration bits */
return -1;
}
}
clkObject.systemClockStatus = SYS_CLK_OPERATION_COMPLETE;
}
}
else
{
/* If the new oscillator is not a PLL source, the one we are running on may
be. So switch first before setting the divisor */
PLIB_OSC_SysClockSelect ( OSC_PLIB_ID, clockSource );
if ( clockSource == SYS_CLK_SOURCE_FRC_BY_DIV )
{
PLIB_OSC_FRCDivisorSelect ( OSC_PLIB_ID, valueToPLLMULT );
}
}
/* Lock it before going back */
SYS_DEVCON_SystemLock ( );
/* Return something which is not equal to '-1'. Let us return the clock source
itself */
return clockSource;
}
