#define SET_BITS(shift, width, reg, val) \
(((reg) & CLRMASK(width, shift)) | (val << (shift)))
#define __inf(msg...)
#define __wrn(msg...) printf(msg)
//#define readl(addr) (*(volatile u32 *) (addr))
//#define writel(val, addr) ((*(volatile u32 *) (addr)) = (val))
#define PLL7_BIAS 0x060000b8
#define PLL8_BIAS 0x060000bc
static u32 de_clk_freq = 0;
clk_pll_para disp_clk_pll_tbl[] ={
PLL_CFG(SYS_CLK_PLL7, CLK_NONE, 0, 0x06000018, 31, 16, 1, 8, 8, 32, 0)
PLL_CFG(SYS_CLK_PLL8, CLK_NONE, 297000000, 0x0600001c, 31, 16, 1, 8, 8, 0, 2)
PLL_CFG(SYS_CLK_PLL10, CLK_NONE, 2376000000UL, 0x06000024, 31, 16, 1, 8, 8, 18, 1)
};
clk_mod_para disp_clk_mod_tbl[] ={
MOD_CFG(MOD_CLK_DETOP, SYS_CLK_PLL10, 396000000, 0x06000588, 7, 0x060005a8, 7, 0x06000490, 31, 32, 0, 0, 4)
MOD_CFG(MOD_CLK_LCD0CH0, SYS_CLK_PLL7, 0, 0x06000588, 0, 0x060005a8, 0, 0x0600049c, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_LCD0CH1, SYS_CLK_PLL7, 0, 0x06000588, 0, 0x060005a8, 0, 0x0600049c, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_LCD1CH0, SYS_CLK_PLL8, 0, 0x06000588, 1, 0x060005a8, 1, 0x060004a0, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_LCD1CH1, SYS_CLK_PLL8, 0, 0x06000588, 1, 0x060005a8, 1, 0x060004a0, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_MIPIDSIS, SYS_CLK_PLL7, 297000000, 0x06000588, 11, 0x060005a8, 11, 0x060004a8, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_MIPIDSIP, SYS_CLK_PLL7, 297000000, 0x06000588, 32, 0x060005a8, 32, 0x060004ac, 31, 32, 0, 32, 0)
MOD_CFG(MOD_CLK_HDMI, SYS_CLK_PLL8, 0, 0x06000588, 5, 0x060005a8, 5, 0x060004b0, 31, 24, 4, 0, 4)
MOD_CFG(MOD_CLK_HDMI_DDC, SYS_CLK_PLL8, 0, 0x06000588, 32, 0x060005a8, 6, 0x060004b4, 31, 32, 0, 32, 0)/* add hdmi reset at hdmi ddc */
MOD_CFG(MOD_CLK_LVDS, CLK_NONE, 0, 0x06000588, 32, 0x060005a8, 3, 0x0, 32, 32, 0, 32, 0)
#define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift))
#define CLRMASK(width, shift) (~(SETMASK(width, shift)))
#define GET_BITS(shift, width, reg) \
(((reg) & SETMASK(width, shift)) >> (shift))
#define SET_BITS(shift, width, reg, val) \
(((reg) & CLRMASK(width, shift)) | (val << (shift)))
#define __inf(msg...)
#define __wrn(msg...) printf(msg)
#define readl(addr) (*(volatile u32 *) (addr))
#define writel(val, addr) ((*(volatile u32 *) (addr)) = (val))
clk_pll_para disp_clk_pll_tbl[] ={
PLL_CFG(SYS_CLK_PLL3, CLK_NONE, 297000000, 0x01c20010, 31, 0, 4, 8, 7, 32, 0, 32, 0)
PLL_CFG(SYS_CLK_PLL10, CLK_NONE, 297000000, 0x01c20048, 31, 0, 4, 8, 7, 32, 0, 32, 0)
PLL_CFG(SYS_CLK_MIPIPLL, SYS_CLK_PLL3, 0, 0x01c20040, 31, 0, 4, 8, 4, 4, 2, 22, 2)
};
clk_mod_para disp_clk_mod_tbl[] ={
MOD_CFG(MOD_CLK_DEBE0, SYS_CLK_PLL10, 145000000, 0x01c20064, 12, 0x01c202c4, 12, 0x01c20100, 26, 0x01c20104, 31, 24, 3, 0, 4)
MOD_CFG(MOD_CLK_DEFE0, SYS_CLK_PLL10, 145000000, 0x01c20064, 14, 0x01c202c4, 14, 0x01c20100, 24, 0x01c2010c, 31, 24, 3, 0, 4)
MOD_CFG(MOD_CLK_LCD0CH0, SYS_CLK_MIPIPLL, 0, 0x01c20064, 4, 0x01c202c4, 4, 0x0, 32, 0x01c20118, 31, 24, 3, 32, 0)
MOD_CFG(MOD_CLK_MIPIDSIS, SYS_CLK_PLL10, 0, 0x01c20060, 1, 0x01c202c0, 1, 0x0, 32, 0x01c20168, 31, 24, 2, 16, 4)
MOD_CFG(MOD_CLK_MIPIDSIP, SYS_CLK_PLL10, 150000000, 0x01c20060, 1, 0x01c202c0, 1, 0x0, 32, 0x01c20168, 15, 8, 2, 0, 4)
MOD_CFG(MOD_CLK_IEPDRC0, SYS_CLK_PLL10, 145000000, 0x01c20064, 25, 0x01c202c4, 25, 0x01c20100, 16, 0x01c20180, 31, 24, 3, 0, 4)
MOD_CFG(MOD_CLK_LVDS, CLK_NONE, 0, 0x0, 32, 0x01c202c8, 0, 0x0, 32, 0x0, 32, 32, 0, 32, 0)
MOD_CFG(MOD_CLK_SAT0, CLK_NONE, 0, 0x01c20064, 26, 0x01c202c4, 26, 0x0, 32, 0x0, 32, 32, 0, 32, 0)
};
u32 pll_enable_count[] = {0, 0, 0};
#define SEP0611_CLK(_id, _parent_id, _name, _flags, _div, _set_rate) \
{ \
.id = _id, \
.parent_id = _parent_id, \
.name = _name, \
.flags = _flags, \
.div = _div, \
.set_rate = _set_rate, \
}
#define PLL_CFG(_f, _r) {.f = _f, .r = _r} //f(frequency), unit: MHz; r(config register value)
#define MHz 1000000UL
static pll_t apll_tab[] = {
PLL_CFG(800*MHz, 0x00010810), // 800MHz
// PLL_CFG(750*MHz, 0x0000F810), // 700MHz
// PLL_CFG(700*MHz, 0x0000E410), // 700MHz
PLL_CFG(650*MHz, 0x0000D410), // 600MHz
// PLL_CFG(600*MHz, 0x0000C410), // 600MHz
// PLL_CFG(550*MHz, 0x0000B410), // 500MHz
PLL_CFG(500*MHz, 0x0000A410), // 500MHz
// PLL_CFG(450*MHz, 0x00009410), // 450MHz
// PLL_CFG(400*MHz, 0x00010802), // 400MHz
// PLL_CFG(350*MHz, 0x00007000), // 350MHz
PLL_CFG(300*MHz, 0x0000C402), // 300MHz
// PLL_CFG(275*MHz, 0x00005800), // 275MHz
// PLL_CFG(250*MHz, 0x0000A402), // 250MHz
// PLL_CFG(200*MHz, 0x00010804), // 200MHz
PLL_CFG(175*MHz, 0x00007002), // 350MHz
// PLL_CFG(150*MHz, 0x0000C406), // 150MHz
