int msm8974_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
u32 count, mode;
int ret = 0;
spin_lock_irqsave(&pll_reg_lock, flags);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Wait for pll to enable. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)) {
WARN("PLL %s didn't lock after enabling it!\n", c->dbg_name);
ret = -ETIMEDOUT;
goto out;
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure the write above goes through before returning. */
mb();
out:
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
static int sr2_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode = readl_relaxed(PLL_MODE_REG(pll));
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
spin_lock_irqsave(&pll_reg_lock, flags);
spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,
pll->spm_ctrl.event_bit, false);
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name);
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
int pll_vote_clk_enable(struct clk *c)
{
u32 ena, count;
unsigned long flags;
struct pll_vote_clk *pllv = to_pll_vote_clk(c);
spin_lock_irqsave(&pll_reg_lock, flags);
ena = readl_relaxed(PLL_EN_REG(pllv));
ena |= pllv->en_mask;
writel_relaxed(ena, PLL_EN_REG(pllv));
spin_unlock_irqrestore(&pll_reg_lock, flags);
/*
* Use a memory barrier since some PLL status registers are
* not within the same 1K segment as the voting registers.
*/
mb();
/* Wait for pll to enable. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask)
return 0;
udelay(1);
}
WARN("PLL %s didn't enable after voting for it!\n", c->dbg_name);
return -ETIMEDOUT;
}
int pll_vote_clk_enable(struct clk *c)
{
u32 ena, count;
unsigned long flags;
struct pll_vote_clk *pllv = to_pll_vote_clk(c);
spin_lock_irqsave(&pll_reg_lock, flags);
ena = readl_relaxed(PLL_EN_REG(pllv));
ena |= pllv->en_mask;
writel_relaxed(ena, PLL_EN_REG(pllv));
spin_unlock_irqrestore(&pll_reg_lock, flags);
mb();
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask)
return 0;
udelay(1);
}
WARN("PLL %s didn't enable after voting for it!\n", c->dbg_name);
return -ETIMEDOUT;
}
int msm8974_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
u32 count, mode;
int ret = 0;
spin_lock_irqsave(&pll_reg_lock, flags);
mode = readl_relaxed(PLL_MODE_REG(pll));
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
mb();
udelay(10);
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)) {
WARN("PLL %s didn't lock after enabling it!\n", c->dbg_name);
ret = -ETIMEDOUT;
goto out;
}
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
mb();
out:
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
int sr_hpm_lp_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
u32 count, mode;
int ret = 0;
spin_lock_irqsave(&pll_reg_lock, flags);
/* Disable PLL bypass mode and de-assert reset. */
mode = PLL_BYPASSNL | PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)) {
WARN("PLL %s didn't lock after enabling it!\n", c->dbg_name);
ret = -ETIMEDOUT;
goto out;
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure the write above goes through before returning. */
mb();
out:
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
int pll_vote_clk_is_enabled(struct clk *c)
{
struct pll_vote_clk *pllv = to_pll_vote_clk(c);
return !!(readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask);
}
int sr_pll_clk_enable(struct clk *c)
{
u32 mode;
int count;
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
u32 status_reg, user_reg, l_reg, m_reg, n_reg, config_reg;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
/* PLL initilazation is similar to HF PLL */
__hf_pll_init(c);
/* Remove SPM HW event */
spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,
pll->spm_ctrl.event_bit, false);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N | PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* A 100us delay required before locking the PLL */
mb();
udelay(100);
/* Wait for the PLL to lock */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)) {
mode = readl_relaxed(PLL_MODE_REG(pll));
status_reg = readl_relaxed(PLL_STATUS_REG(pll));
user_reg = readl_relaxed(PLL_CONFIG_REG(pll));
config_reg = readl_relaxed(PLL_CFG_CTL_REG(pll));
l_reg = readl_relaxed(PLL_L_REG(pll));
m_reg = readl_relaxed(PLL_M_REG(pll));
n_reg = readl_relaxed(PLL_N_REG(pll));
pr_err("PLL %s didn't lock after enabling for L value 0x%x!\n",
c->dbg_name, l_reg);
pr_err("mode register is 0x%x\n", mode);
pr_err("status register is 0x%x\n", status_reg);
pr_err("user control register is 0x%x\n", user_reg);
pr_err("config control register is 0x%x\n", config_reg);
pr_err("L value register is 0x%x\n", l_reg);
pr_err("M value register is 0x%x\n", m_reg);
pr_err("N value control register is 0x%x\n", n_reg);
if (pll->spm_ctrl.spm_base)
pr_err("L2 spm_force_event_en 0x%x\n",
readl_relaxed(pll->spm_ctrl.spm_base +
SPM_FORCE_EVENT));
panic("PLL %s didn't lock after enabling it!\n", c->dbg_name);
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return 0;
}
static int variable_rate_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode, testlo;
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
u32 mode_lock;
u64 time;
bool early_lock = false;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
__variable_rate_pll_init(c);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Set test control bits as required by HW doc */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(pll->vals.test_ctl_lo_val,
PLL_TEST_CTL_LO_REG(pll));
/* Enable test_ctl debug */
mode |= BIT(3);
writel_relaxed(mode, PLL_MODE_REG(pll));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0xC0;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Use 10us to be sure.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* 5us delay mandated by HPG. However, put in a 200us delay here.
* This is to address possible locking issues with the PLL exhibit
* early "transient" locks about 16us from this point. With this
* higher delay, we avoid running into those transients.
*/
mb();
udelay(200);
/* Clear test control bits */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll));
time = sched_clock();
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) {
udelay(1);
/*
* Check again to be sure. This is to avoid
* breaking too early if there is a "transient"
* lock.
*/
if ((readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
break;
else
early_lock = true;
}
udelay(1);
}
time = sched_clock() - time;
mode_lock = readl_relaxed(PLL_STATUS_REG(pll));
if (!(mode_lock & lockmask)) {
pr_err("PLL lock bit detection total wait time: %lld ns", time);
pr_err("PLL %s didn't lock after enabling for L value 0x%x!\n",
c->dbg_name, readl_relaxed(PLL_L_REG(pll)));
pr_err("mode register is 0x%x\n",
readl_relaxed(PLL_STATUS_REG(pll)));
pr_err("user control register is 0x%x\n",
readl_relaxed(PLL_CONFIG_REG(pll)));
pr_err("config control register is 0x%x\n",
readl_relaxed(PLL_CFG_CTL_REG(pll)));
pr_err("test control high register is 0x%x\n",
readl_relaxed(PLL_TEST_CTL_HI_REG(pll)));
pr_err("test control low register is 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)));
pr_err("early lock? %s\n", early_lock ? "yes" : "no");
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0x40;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0x80;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0xC0;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
panic("failed to lock %s PLL\n", c->dbg_name);
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
static int hf_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode;
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
u32 status_reg, user_reg, l_reg, m_reg, n_reg, config_reg;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
__hf_pll_init(c);
/* Remove SPM HW event */
spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,
pll->spm_ctrl.event_bit, false);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Use 10us to be sure.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* A 50us delay required before locking the PLL. */
mb();
udelay(50);
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) {
udelay(1);
/*
* Check again to be sure. This is to avoid
* breaking too early if there is a "transient"
* lock.
*/
if ((readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
break;
}
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)) {
mode = readl_relaxed(PLL_MODE_REG(pll));
status_reg = readl_relaxed(PLL_STATUS_REG(pll));
user_reg = readl_relaxed(PLL_CONFIG_REG(pll));
config_reg = readl_relaxed(PLL_CFG_CTL_REG(pll));
l_reg = readl_relaxed(PLL_L_REG(pll));
m_reg = readl_relaxed(PLL_M_REG(pll));
n_reg = readl_relaxed(PLL_N_REG(pll));
pr_err("PLL %s didn't lock after enabling for L value 0x%x!\n",
c->dbg_name, l_reg);
pr_err("mode register is 0x%x\n", mode);
pr_err("status register is 0x%x\n", status_reg);
pr_err("user control register is 0x%x\n", user_reg);
pr_err("config control register is 0x%x\n", config_reg);
pr_err("L value register is 0x%x\n", l_reg);
pr_err("M value register is 0x%x\n", m_reg);
pr_err("N value control register is 0x%x\n", n_reg);
if (pll->spm_ctrl.spm_base)
pr_err("L2 spm_force_event_en 0x%x\n",
readl_relaxed(pll->spm_ctrl.spm_base +
SPM_FORCE_EVENT));
panic("PLL %s didn't lock after enabling it!\n", c->dbg_name);
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
static int variable_rate_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode;
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
__variable_rate_pll_init(c);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Set test control bits as required by HW doc */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(pll->vals.test_ctl_lo_val,
PLL_TEST_CTL_LO_REG(pll));
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Use 10us to be sure.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* 5us delay mandated by HPG. Use 10 to be sure. */
mb();
udelay(10);
/* Clear test control bits */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll));
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name);
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
