static void ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "ucf-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; pcd->pcd_caps = UCF_PMC_CAPS; pcd->pcd_class = PMC_CLASS_UCF; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = ucf_allocate_pmc; pcd->pcd_config_pmc = ucf_config_pmc; pcd->pcd_describe = ucf_describe; pcd->pcd_get_config = ucf_get_config; pcd->pcd_get_msr = NULL; pcd->pcd_pcpu_fini = uncore_pcpu_noop; pcd->pcd_pcpu_init = uncore_pcpu_noop; pcd->pcd_read_pmc = ucf_read_pmc; pcd->pcd_release_pmc = ucf_release_pmc; pcd->pcd_start_pmc = ucf_start_pmc; pcd->pcd_stop_pmc = ucf_stop_pmc; pcd->pcd_write_pmc = ucf_write_pmc; md->pmd_npmc += npmc; }
void pmc_uncore_finalize(struct pmc_mdep *md) { PMCDBG0(MDP,INI,1, "uncore-finalize"); free(uncore_pcpu, M_PMC); uncore_pcpu = NULL; }
int pmc_p4_initialize(struct pmc_mdep *md, int ncpus) { struct pmc_classdep *pcd; struct p4_event_descr *pe; KASSERT(md != NULL, ("[p4,%d] md is NULL", __LINE__)); KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, ("[p4,%d] Initializing non-intel processor", __LINE__)); PMCDBG0(MDP,INI,1, "p4-initialize"); /* Allocate space for pointers to per-cpu descriptors. */ p4_pcpu = malloc(sizeof(*p4_pcpu) * ncpus, M_PMC, M_ZERO | M_WAITOK); /* Fill in the class dependent descriptor. */ pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4]; switch (md->pmd_cputype) { case PMC_CPU_INTEL_PIV: pcd->pcd_caps = P4_PMC_CAPS; pcd->pcd_class = PMC_CLASS_P4; pcd->pcd_num = P4_NPMCS; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = 40; pcd->pcd_allocate_pmc = p4_allocate_pmc; pcd->pcd_config_pmc = p4_config_pmc; pcd->pcd_describe = p4_describe; pcd->pcd_get_config = p4_get_config; pcd->pcd_get_msr = p4_get_msr; pcd->pcd_pcpu_fini = p4_pcpu_fini; pcd->pcd_pcpu_init = p4_pcpu_init; pcd->pcd_read_pmc = p4_read_pmc; pcd->pcd_release_pmc = p4_release_pmc; pcd->pcd_start_pmc = p4_start_pmc; pcd->pcd_stop_pmc = p4_stop_pmc; pcd->pcd_write_pmc = p4_write_pmc; md->pmd_pcpu_fini = NULL; md->pmd_pcpu_init = NULL; md->pmd_intr = p4_intr; md->pmd_npmc += P4_NPMCS; /* model specific configuration */ if ((cpu_id & 0xFFF) < 0xF27) { /* * On P4 and Xeon with CPUID < (Family 15, * Model 2, Stepping 7), only one ESCR is * available for the IOQ_ALLOCATION event. */ pe = p4_find_event(PMC_EV_P4_IOQ_ALLOCATION); pe->pm_escrs[1] = P4_ESCR_NONE; } break; default: KASSERT(0,("[p4,%d] Unknown CPU type", __LINE__)); return ENOSYS; } return (0); }