void configure_gpio_i2c_pins(uint32_t instance)
{
PORT_HAL_SetMuxMode(PORTE,24u,kPortMuxAsGpio);
PORT_HAL_SetMuxMode(PORTE,25u,kPortMuxAsGpio);
}
void configure_gpio_pins(uint32_t instance)
{
switch(instance) {
case PORTA_IDX: /* PORTA_IDX */
/* Affects PORTA_PCR4 register */
PORT_HAL_SetPassiveFilterCmd(PORTA,4u,false);
PORT_HAL_SetMuxMode(PORTA,4u,kPortMuxAsGpio);
PORT_HAL_SetPullMode(PORTA,4u,kPortPullUp);
PORT_HAL_SetPullCmd(PORTA,4u,true);
break;
case PORTB_IDX: /* PORTB_IDX */
/* Affects PORTB_PCR21 register */
PORT_HAL_SetDriveStrengthMode(PORTB,21u,kPortLowDriveStrength);
PORT_HAL_SetMuxMode(PORTB,21u,kPortMuxAsGpio);
PORT_HAL_SetSlewRateMode(PORTB,21u,kPortSlowSlewRate);
/* Affects PORTB_PCR22 register */
PORT_HAL_SetDriveStrengthMode(PORTB,22u,kPortLowDriveStrength);
PORT_HAL_SetMuxMode(PORTB,22u,kPortMuxAsGpio);
PORT_HAL_SetSlewRateMode(PORTB,22u,kPortSlowSlewRate);
break;
case PORTC_IDX: /* PORTC_IDX */
/* Affects PORTC_PCR0 register */
PORT_HAL_SetMuxMode(PORTC,0u,kPortMuxAsGpio);
/* Affects PORTC_PCR6 register */
PORT_HAL_SetPassiveFilterCmd(PORTC,6u,false);
PORT_HAL_SetMuxMode(PORTC,6u,kPortMuxAsGpio);
PORT_HAL_SetPullMode(PORTC,6u,kPortPullUp);
PORT_HAL_SetPullCmd(PORTC,6u,true);
/* Affects PORTC_PCR8 register */
PORT_HAL_SetMuxMode(PORTC,8u,kPortMuxAsGpio);
/* Affects PORTC_PCR9 register */
PORT_HAL_SetMuxMode(PORTC,9u,kPortMuxAsGpio);
/* Affects PORTC_PCR12 register */
PORT_HAL_SetMuxMode(PORTC,12u,kPortMuxAsGpio);
/* Affects PORTC_PCR13 register */
PORT_HAL_SetMuxMode(PORTC,13u,kPortMuxAsGpio);
break;
case PORTE_IDX: /* PORTE_IDX */
/* Affects PORTE_PCR6 register */
PORT_HAL_SetMuxMode(PORTE,6u,kPortMuxAsGpio);
/* Affects PORTE_PCR26 register */
PORT_HAL_SetDriveStrengthMode(PORTE,26u,kPortLowDriveStrength);
PORT_HAL_SetMuxMode(PORTE,26u,kPortMuxAsGpio);
PORT_HAL_SetSlewRateMode(PORTE,26u,kPortSlowSlewRate);
break;
default:
break;
}
}
void configure_spi_cs1_pins(uint32_t instance)
{
PORT_HAL_SetMuxMode(PORTD,4u,kPortMuxAsGpio);
}
void setup_uart_pins(port_mux_t mux)
{
PORT_HAL_SetMuxMode(PORTA,1u, mux);
PORT_HAL_SetMuxMode(PORTA,2u, mux);
}
void configure_gpio_pins(uint32_t instance)
{
switch(instance) {
case 1: /* PTB */
/* PORTB_PCR0 */
PORT_HAL_SetMuxMode(PORTB_BASE,0u,kPortMuxAsGpio);
/* PORTB_PCR1 */
PORT_HAL_SetMuxMode(PORTB_BASE,1u,kPortMuxAsGpio);
/* PORTB_PCR6 */
PORT_HAL_SetMuxMode(PORTB_BASE,6u,kPortMuxAsGpio);
/* PORTB_PCR8 */
PORT_HAL_SetMuxMode(PORTB_BASE,8u,kPortMuxAsGpio);
break;
case 2: /* PTC */
/* PORTC_PCR6 */
PORT_HAL_SetMuxMode(PORTC_BASE,6u,kPortMuxAsGpio);
/* PORTC_PCR7 */
PORT_HAL_SetMuxMode(PORTC_BASE,7u,kPortMuxAsGpio);
/* PORTC_PCR8 */
PORT_HAL_SetMuxMode(PORTC_BASE,8u,kPortMuxAsGpio);
/* PORTC_PCR9 */
PORT_HAL_SetMuxMode(PORTC_BASE,9u,kPortMuxAsGpio);
break;
case 3: /* PTD */
/* PORTD_PCR4 */
PORT_HAL_SetMuxMode(PORTD_BASE,4u,kPortMuxAsGpio);
/* PORTD_PCR5 */
PORT_HAL_SetMuxMode(PORTD_BASE,5u,kPortMuxAsGpio);
/* PORTD_PCR6 */
PORT_HAL_SetMuxMode(PORTD_BASE,6u,kPortMuxAsGpio);
/* PORTD_PCR7 */
PORT_HAL_SetMuxMode(PORTD_BASE,7u,kPortMuxAsGpio);
break;
default:
break;
}
}
void configure_rtc_pins(uint32_t instance)
{
/* PORTE_PCR26 */
PORT_HAL_SetMuxMode(PORTE,26u,kPortMuxAlt6);
}
void configure_rtc_pins(uint32_t instance)
{
/* Affects PORTE_PCR0 register */
PORT_HAL_SetMuxMode(PORTE,0u,kPortMuxAlt4);
}
void configure_dac_pin(uint32_t instance)
{
PORT_HAL_SetMuxMode(PORTE_BASE, 30u, kPortPinDisabled);
}
void configure_rtc_pins(uint32_t instance)
{
/* PORTB_PCR13 */
PORT_HAL_SetMuxMode(PORTB,13u,kPortMuxAlt3);
}
/*************************************************************************
* Function Name: FTM0_init
* Parameters: none
* Return: none
* Description: FlexTimer 0 initialization
*************************************************************************/
void FTM0_init(void)
{
FTM_HAL_SetWriteProtectionCmd(FTM0_BASE_PTR, false);//false: Write-protection is disabled
FTM_HAL_Enable(FTM0_BASE_PTR, true);//true: all registers including FTM-specific registers are available
FTM_HAL_SetCounterInitVal(FTM0_BASE_PTR, (uint16_t)(-PWM_MODULO/2));
FTM_HAL_SetMod(FTM0_BASE_PTR, (uint16_t)PWM_MODULO/2-1); // 20 kHz
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 0, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 1, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 2, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 3, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 4, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 5, 2);
// output mask updated on PWM synchronization (not on rising edge of clock)
FTM_HAL_SetMaxLoadingCmd(FTM0_BASE_PTR, true);//True to enable minimum loading point
FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM0_BASE_PTR, 1);//true if OUTMASK register is updated only by PWM sync\n
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 0, true);//True to enable PWM synchronization
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 0, true);//True to enable deadtime insertion, false to disable
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 0, true);//True to enable complementary mode, false to disable
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 0, true);// True to enable channel pair to combine, false to disable
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 2, true);
// High transistors have negative polarity (MC33927/37)
FTM_HAL_SetDeadtimePrescale(FTM0_BASE_PTR, kFtmDivided1);
FTM_HAL_SetDeadtimeCount(FTM0_BASE_PTR, FTM_DEADTIME_DTVAL(63)); // DTVAL - deadtime value (0-63): deadtime period = DTPS x DTVAL
FTM_HAL_SetInitTriggerCmd(FTM0_BASE_PTR, true);//True to enable, false to disable
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 0, 1);
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 2, 1);
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 4, 1);
/* Following line configures:
- enhanced PWM synchronization, FTM counter reset on SW sync
- output SW control / polarity registers updated on PWM synchronization (not on rising edge of clock)
- output SW control/inverting(swap)/mask registers updated from buffers on SW synchronization */
FTM_HAL_SetPwmSyncModeCmd(FTM0_BASE_PTR, true);// true means use Enhanced PWM synchronization\n
FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM0_BASE_PTR, true);//true means SWOCTRL register is updated by PWM synch\n
FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM0_BASE_PTR, true);//true means INVCTRL register is updated by PWM synch\n
FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 0, 1);//Sets the FTM peripheral timer channel output mask.
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 1, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 2, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 3, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 4, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 5, 1);
FTM_HAL_SetCounter(FTM0_BASE_PTR, 1U); // update of FTM settings
// no ISR, counting up, system clock, divide by 1
FTM_HAL_SetClockSource(FTM0_BASE_PTR, kClock_source_FTM_SystemClk);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 0, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 1,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 2, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 3,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 4, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 5,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetSoftwareTriggerCmd(FTM0_BASE_PTR, 1);
FTM_HAL_SetPwmLoadCmd(FTM0_BASE_PTR, 1);
// FTM0 PWM output pins
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 1, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 3, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 4, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 4, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 5, kPortMuxAlt4);
#if defined(KV10Z7_SERIES)
PORT_HAL_SetMuxMode(PORTE_BASE_PTR, 25, kPortMuxAlt3);
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 2, kPortMuxAlt4);
#endif
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 1, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 3, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 4, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 4, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 5, kGpioDigitalOutput);
#if defined(KV10Z7_SERIES)
GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 25, kGpioDigitalOutput);
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput);
#endif
}
/*************************************************************************
* Function Name: SPI0_init
* Parameters: none
* Return: none
* Description: SPI initialization
*************************************************************************/
void SPI0_init(void)
{
dspi_baud_rate_divisors_t divisors;
divisors.doubleBaudRate = 0;
divisors.baudRateDivisor = 3;
divisors.prescaleDivisor = 3;
dspi_data_format_config_t config;
config.clkPhase = kDspiClockPhase_SecondEdge;
config.bitsPerFrame = 8;
config.clkPolarity = kDspiClockPolarity_ActiveHigh;
config.direction = kDspiMsbFirst;
#if defined(KV10Z7_SERIES)
PORT_HAL_SetMuxMode(PORTC_BASE_PTR,2,kPortMuxAsGpio);// MC33937 RESET
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR,7,kPortMuxAsGpio);// MC33937 DRV_EN
GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 7, kGpioDigitalOutput);
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
PORT_HAL_SetMuxMode(PORTE_BASE_PTR,29,kPortMuxAsGpio);// MC33937 DRV_EN
GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 29, kGpioDigitalOutput);
#endif
GPIO_HAL_SetPinOutput(GPIOC_BASE_PTR, 2);//MC33937_RESET_HIGH;
#if defined(KV10Z7_SERIES)
GPIO_HAL_SetPinOutput(GPIOD_BASE_PTR, 7);//MC33937_ENABLE_HIGH;
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
GPIO_HAL_SetPinOutput(GPIOE_BASE_PTR, 29);
#endif
DSPI_HAL_StopTransfer(SPI0_BASE_PTR);// halt SPI before SPI setting
DSPI_HAL_Enable(SPI0_BASE_PTR);//Enables the DSPI peripheral and sets the MCR MDIS to 0.
DSPI_HAL_SetMasterSlaveMode(SPI0_BASE_PTR, kDspiMaster);//Enable Master Mode
DSPI_HAL_SetPcsPolarityMode(SPI0_BASE_PTR, kDspiPcs0,kDspiPcs_ActiveLow);//The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
DSPI_HAL_SetFifoCmd(SPI0_BASE_PTR, false, false);//Disable the DSPI FIFOs.
DSPI_HAL_PresetTransferCount(SPI0_BASE_PTR, 0x0000);//Pre-sets the transfer count.
DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,3,0, kDspiPcsToSck); // CTAR0 selection option for master or slave mode
DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,2,0, kDspiLastSckToPcs);
DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,0,2, kDspiAfterTransfer);
DSPI_HAL_SetBaudDivisors(SPI0_BASE_PTR, kDspiCtar0, &divisors);
DSPI_HAL_SetDataFormat(SPI0_BASE_PTR, kDspiCtar0, &config);
DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxComplete);///*!< TCF status/interrupt enable */
DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiEndOfQueue);///*!< EOQF status/interrupt enable*/
DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoUnderflow);///*!< TFUF status/interrupt enable*/
DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoFillRequest);///*!< TFFF status/interrupt enable*/
DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiRxFifoOverflow);///*!< RFOF status/interrupt enable*/
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxComplete, false);/*!< TCF status/interrupt disable */
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiEndOfQueue, false);/*!< EOQF status/interrupt disable */
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoUnderflow, false);/*!< TFUF status/interrupt disable*/
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoFillRequest, false);/*!< TFFF status/interrupt disable*/
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoOverflow, false);/*!< RFOF status/interrupt disable*/
DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoDrainRequest, false);/*!< RFDF status/interrupt disable*/
DSPI_HAL_StartTransfer(SPI0_BASE_PTR);// Starts the DSPI transfers, clears HALT bit in MCR.
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 3, kPortMuxAlt2);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 2, kPortMuxAlt2);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 0, kPortMuxAlt7);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 5, kPortMuxAlt2);
}
void setup_uart_pins(port_mux_t mux)
{
/* UART1 */
PORT_HAL_SetMuxMode(PORTE,0u,mux);
PORT_HAL_SetMuxMode(PORTE,1u,mux);
}
/*!
* @brief Main function
*/
int main (void)
{
/* enable clock for PORTs */
CLOCK_SYS_EnablePortClock(PORTA_IDX);
//CLOCK_SYS_EnablePortClock(PORTB_IDX);
CLOCK_SYS_EnablePortClock(PORTC_IDX);
CLOCK_SYS_EnablePortClock(PORTD_IDX);
CLOCK_SYS_EnablePortClock(PORTE_IDX);
/* Set allowed power mode, allow all. */
SMC_HAL_SetProtection(SMC, kAllowPowerModeAll);
/* Set system clock configuration. */
CLOCK_SYS_SetConfiguration(&g_defaultClockConfigVlpr);
/* Initialize LPTMR */
lptmr_state_t lptmrState;
LPTMR_DRV_Init(LPTMR0_IDX, &lptmrState, &g_lptmrConfig);
LPTMR_DRV_SetTimerPeriodUs(LPTMR0_IDX, 100000);
LPTMR_DRV_InstallCallback(LPTMR0_IDX, lptmr_call_back);
/* Initialize DMA */
dma_state_t dma_state;
DMA_DRV_Init(&dma_state);
/* Initialize PIT */
PIT_DRV_Init(0, false);
PIT_DRV_InitChannel(0, 0, &g_pitChan0);
/* Initialize CMP */
CMP_DRV_Init(0, &g_cmpState, &g_cmpConf);
CMP_DRV_ConfigDacChn(0, &g_cmpDacConf);
PORT_HAL_SetMuxMode(g_portBase[GPIOC_IDX], 0, kPortMuxAlt5);
CMP_DRV_Start(0);
/* Buttons */
GPIO_DRV_InputPinInit(&g_switch1);
GPIO_DRV_InputPinInit(&g_switch2);
GPIO_DRV_InputPinInit(&g_switchUp);
GPIO_DRV_InputPinInit(&g_switchDown);
GPIO_DRV_InputPinInit(&g_switchLeft);
GPIO_DRV_InputPinInit(&g_switchRight);
GPIO_DRV_InputPinInit(&g_switchSelect);
/* Start LPTMR */
LPTMR_DRV_Start(LPTMR0_IDX);
/* Setup LPUART1 */
LPUART_DRV_Init(1, &g_lpuartState, &g_lpuartConfig);
LPUART_DRV_InstallRxCallback(1, lpuartRxCallback, rxBuff, NULL, true);
LPUART_DRV_InstallTxCallback(1, lpuartTxCallback, NULL, NULL);
LPUART_BWR_CTRL_TXINV(g_lpuartBase[1], 1);
PORT_HAL_SetMuxMode(g_portBase[GPIOE_IDX], 0, kPortMuxAlt3);
PORT_HAL_SetMuxMode(g_portBase[GPIOE_IDX], 1, kPortMuxAlt3);
/* Setup FlexIO for the WS2812B */
FLEXIO_Type *fiobase = g_flexioBase[0];
CLOCK_SYS_SetFlexioSrc(0, kClockFlexioSrcMcgIrClk);
FLEXIO_DRV_Init(0, &g_flexioConfig);
FLEXIO_HAL_ConfigureTimer(fiobase, 0, &g_timerConfig);
FLEXIO_HAL_ConfigureShifter(fiobase, 0, &g_shifterConfig);
PORT_HAL_SetMuxMode(g_portBase[GPIOE_IDX], 20, kPortMuxAlt6);
FLEXIO_DRV_Start(0);
FLEXIO_HAL_SetShifterStatusDmaCmd(fiobase, 1, true);
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0FlexIOChannel0,
&g_fioChan);
DMA_DRV_RegisterCallback(&g_fioChan, fioDmaCallback, NULL);
/* Connect buzzer to TPM0_CH3 */
PORT_HAL_SetMuxMode(g_portBase[GPIOE_IDX], 30, kPortMuxAlt3);
tpm_general_config_t tmpConfig = {
.isDBGMode = false,
.isGlobalTimeBase = false,
.isTriggerMode = false,
.isStopCountOnOveflow = false,
.isCountReloadOnTrig = false,
.triggerSource = kTpmTrigSel0,
};
TPM_DRV_Init(0, &tmpConfig);
TPM_DRV_SetClock(0, kTpmClockSourceModuleMCGIRCLK, kTpmDividedBy1);
/* Blank LED just in case, saves power */
led(0x00, 0x00, 0x00);
/* Init e-paper display */
EPD_Init();
/* Throw up first image */
int ret = EPD_Draw(NULL, images[current_image]);
if (-1 == ret) {
led(0xff, 0x00, 0x00);
} else if (-2 == ret) {
led(0xff, 0xff, 0x00);
} else if (-3 == ret) {
led(0x00, 0x00, 0xff);
} else {
led(0x00, 0xff, 0x00);
}
blank_led = 30;
/* Deinit so we can mess around on the bus pirate */
//EPD_Deinit();
/* We're done, everything else is triggered through interrupts */
for(;;) {
if (cue_next_image) {
int old_image = current_image;
current_image = (current_image + 1) % image_count;
EPD_Draw(images[old_image], images[current_image]);
cue_next_image = 0;
}
#ifndef DEBUG
SMC_HAL_SetMode(SMC, &g_idlePowerMode);
#endif
}
}
void configure_lcd_pins(uint32_t instance)
{
PORT_HAL_SetMuxMode(PORTE, 20u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTE, 21u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTB, 18u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTB, 19u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTC, 0u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTC, 4u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTC, 6u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTC, 7u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD, 0u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD, 2u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD, 3u, kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD, 4u, kPortPinDisabled);
}
void configure_enet_pins(uint32_t instance)
{
/* Affects PORTC_PCR16 register */
PORT_HAL_SetMuxMode(PORTC,16u,kPortMuxAlt4);
/* Affects PORTC_PCR17 register */
PORT_HAL_SetMuxMode(PORTC,17u,kPortMuxAlt4);
/* Affects PORTC_PCR18 register */
PORT_HAL_SetMuxMode(PORTC,18u,kPortMuxAlt4);
/* Affects PORTC_PCR19 register */
PORT_HAL_SetMuxMode(PORTC,19u,kPortMuxAlt4);
/* Affects PORTB_PCR1 register */
PORT_HAL_SetMuxMode(PORTB,1u,kPortMuxAlt4);
/* Affects PORTB_PCR0 register */
PORT_HAL_SetMuxMode(PORTB,0u,kPortMuxAlt4);
PORT_HAL_SetOpenDrainCmd(PORTB,0u,true);
PORT_HAL_SetPullMode(PORTB,0u,kPortPullUp);
PORT_HAL_SetPullCmd(PORTB,0u,true);
/* Affects PORTA_PCR13 register */
PORT_HAL_SetMuxMode(PORTA,13u,kPortMuxAlt4);
/* Affects PORTA_PCR12 register */
PORT_HAL_SetMuxMode(PORTA,12u,kPortMuxAlt4);
/* Affects PORTA_PCR14 register */
PORT_HAL_SetMuxMode(PORTA,14u,kPortMuxAlt4);
/* Affects PORTA_PCR5 register */
PORT_HAL_SetMuxMode(PORTA,5u,kPortMuxAlt4);
/* Affects PORTA_PCR16 register */
PORT_HAL_SetMuxMode(PORTA,16u,kPortMuxAlt4);
/* Affects PORTA_PCR17 register */
PORT_HAL_SetMuxMode(PORTA,17u,kPortMuxAlt4);
/* Affects PORTA_PCR15 register */
PORT_HAL_SetMuxMode(PORTA,15u,kPortMuxAlt4);
/* Affects PORTA_PCR28 register */
PORT_HAL_SetMuxMode(PORTA,28u,kPortMuxAlt4);
}
int main (void)
{
uint8_t msg;
uint32_t timeout = 0;
uint32_t var;
volatile uint16_t count;
OSA_Init();
hardware_init();
dbg_uart_init();
configure_spi_pins(HW_SPI0);
printf("dspi_edma_test_slave\r\n");
printf("\r\nDemo started...\r\n");
// Initialize configuration
edma_init();
edma_dspi_rx_setup(kEDMAChannel2, (uint32_t)&g_slaveRxBuffer);
dspi_slave_setup(HW_SPI0, SPI_BAUDRATE);
printf("Press space bar to begin.\r\n");
msg = 'A';
while(msg != ' ')
{
msg = getchar();
}
printf("\r\nDemo started...\r\n");
// Slave only have PCS0
PORT_HAL_SetMuxMode(PORTC_BASE, 0u, kPortMuxAlt7);
// Enable eDMA channels requests to initiate DSPI transfers.
EDMA_HAL_SetDmaRequestCmd(DMA_BASE, kEDMAChannel2, true);
DSPI_HAL_StartTransfer(SPI0_BASE);
// Waiting transfer complete
printf("waiting transfer complete...\r\n");
while((bReceivedFlag == false) & (timeout < 50))
{
OSA_TimeDelay(100);
timeout++;
}
if(bReceivedFlag == false)
{
printf("No date received, please check connections\r\n");
}
printf("received data:\r\n");
for(count = 0; count < TEST_DATA_LEN; count++)
{
var = g_slaveRxBuffer[count];
printf("%08X\t", (unsigned int)var);
if((count + 1) % 4 == 0)
{
printf("\r\n");
}
}
printf("\r\nEnd of demo.\r\n");
}
/*****************************************************************************
* EEPROM_Init
*
* Initializes the EEPROM peripheral
*
*****************************************************************************/
ee_err_t EEPROM_Init(void)
{
ee_err_t retval;
spiBusConfig_t spiConfig = {
.bitsPerSec = 2000000,
.master = TRUE,
.clkActiveHigh = TRUE,
.clkPhaseFirstEdge = TRUE,
.MsbFirst = TRUE
};
#if gEepromWriteEnable_d
uint32_t i;
// Mark Flash as Unerased
for(i = 0; i < 64; i++)
mEepromEraseBitmap[i] = 0;
#endif
if(Spi_Init(gEepromSpiInstance_c, &mEepromSpiState, NULL, NULL) != spiSuccess)
{
return ee_error;
}
if(Spi_Configure(gEepromSpiInstance_c, &spiConfig) != spiSuccess)
{
return ee_error;
}
GPIO_DRV_OutputPinInit(&mEepromSpiCsCfg);
PORT_HAL_SetMuxMode(g_portBase[GPIO_EXTRACT_PORT(gEepromSpiCsPin_d)],
GPIO_EXTRACT_PIN(gEepromSpiCsPin_d),
kPortMuxAsGpio);
gEepromDeassertCS_d();
return ee_ok;
}
/*****************************************************************************
* EEPROM_ChipErase
*
* Erase all memory to 0xFF
*
*****************************************************************************/
ee_err_t EEPROM_ChipErase(void)
{
// make sure the write process is ready
while(EEPROM_GetWriteReady() != ee_ok);
return EEPROM_SendCmd(EEPROM_CMD_ERASE_BULK, EEPROM_CMD_END);
}
/*****************************************************************************
* EEPROM_EraseBlock
*
* Erase a block of memory to 0xFF
*
*****************************************************************************/
ee_err_t EEPROM_EraseBlock(uint32_t Addr, uint32_t size)
{
ee_err_t status = ee_ok;
if(size != EEPROM_SECTOR_SIZE)
{
return ee_error;
}
// make sure the write process is ready
while(EEPROM_GetWriteReady() != ee_ok);
// send the command
status |= EEPROM_SendCmd( EEPROM_CMD_ERASE_SECTOR, EEPROM_CMD_CNT );
// send the address
status |= EEPROM_SendAddress(Addr);
if (status == ee_ok)
{
gEepromDeassertCS_d();
return ee_ok;
}
else
{
return ee_error;
}
}
void configure_spi_pins(uint32_t instance)
{
switch(instance) {
case 0: /* SPI0 */
/* PORTD_PCR0 */
PORT_HAL_SetMuxMode(PORTD_BASE,0u,kPortMuxAlt2);
/* PORTD_PCR3 */
PORT_HAL_SetMuxMode(PORTD_BASE,3u,kPortMuxAlt2);
/* PORTD_PCR1 */
PORT_HAL_SetMuxMode(PORTD_BASE,1u,kPortMuxAlt2);
/* PORTD_PCR2 */
PORT_HAL_SetMuxMode(PORTD_BASE,2u,kPortMuxAlt2);
break;
case 1: /* SPI1 */
/* PORTB_PCR10 */
PORT_HAL_SetMuxMode(PORTB_BASE,10u,kPortMuxAlt2);
/* PORTB_PCR17 */
PORT_HAL_SetMuxMode(PORTB_BASE,17u,kPortMuxAlt2);
/* PORTB_PCR11 */
PORT_HAL_SetMuxMode(PORTB_BASE,11u,kPortMuxAlt2);
/* PORTB_PCR16 */
PORT_HAL_SetMuxMode(PORTB_BASE,16u,kPortMuxAlt2);
break;
case 2: /* SPI2 */
/* PORTD_PCR11 */
PORT_HAL_SetMuxMode(PORTD_BASE,11u,kPortMuxAlt2);
/* PORTD_PCR12 */
PORT_HAL_SetMuxMode(PORTD_BASE,12u,kPortMuxAlt2);
/* PORTD_PCR13 */
PORT_HAL_SetMuxMode(PORTD_BASE,13u,kPortMuxAlt2);
/* PORTD_PCR14 */
PORT_HAL_SetMuxMode(PORTD_BASE,14u,kPortMuxAlt2);
break;
default:
break;
}
}
void configure_gpio_pins(uint32_t instance)
{
switch(instance) {
case PORTA_IDX: /* PTA */
/* PORTA_PCR4 */
PORT_HAL_SetMuxMode(PORTA,4u,kPortMuxAsGpio);
/* PORTA_PCR18 */
PORT_HAL_SetMuxMode(PORTA,18u,kPortMuxAsGpio);
/* PORTA_PCR19 */
PORT_HAL_SetMuxMode(PORTA,19u,kPortMuxAsGpio);
break;
case PORTB_IDX: /* PTB */
/* PORTB_PCR0 */
PORT_HAL_SetMuxMode(PORTB,0u,kPortMuxAsGpio);
break;
case PORTC_IDX: /* PTC */
/* PORTC_PCR3 */
PORT_HAL_SetMuxMode(PORTC,3u,kPortMuxAsGpio);
/* PORTC_PCR4 */
PORT_HAL_SetMuxMode(PORTC,4u,kPortMuxAsGpio);
break;
case PORTD_IDX: /* PTD */
/* PORTD_PCR0 */
PORT_HAL_SetMuxMode(PORTD,0u,kPortMuxAsGpio);
/* PORTD_PCR4 */
PORT_HAL_SetMuxMode(PORTD,4u,kPortMuxAsGpio);
/* PORTD_PCR5 */
PORT_HAL_SetMuxMode(PORTD,5u,kPortMuxAsGpio);
/* PORTD_PCR6 */
PORT_HAL_SetMuxMode(PORTD,6u,kPortMuxAsGpio);
/* PORTD_PCR7 */
PORT_HAL_SetMuxMode(PORTD,7u,kPortMuxAsGpio);
break;
case PORTE_IDX: /* PTE */
/* PORTE_PCR16 */
PORT_HAL_SetMuxMode(PORTE,16u,kPortMuxAsGpio);
/* PORTE_PCR17 */
PORT_HAL_SetMuxMode(PORTE,17u,kPortMuxAsGpio);
/* PORTE_PCR30 */
PORT_HAL_SetMuxMode(PORTE,30u,kPortMuxAsGpio);
break;
default:
break;
}
}
void de_init_pins(void)
{
/* PORTB_PCR0 */
PORT_HAL_SetMuxMode(PORTB_BASE,0u,kPortPinDisabled);
/* PORTB_PCR1 */
PORT_HAL_SetMuxMode(PORTB_BASE,1u,kPortPinDisabled);
/* PORTB_PCR6 */
PORT_HAL_SetMuxMode(PORTB_BASE,6u,kPortPinDisabled);
/* PORTB_PCR8 */
PORT_HAL_SetMuxMode(PORTB_BASE,8u,kPortPinDisabled);
/* PORTC_PCR8 */
PORT_HAL_SetMuxMode(PORTC_BASE,8u,kPortPinDisabled);
/* PORTC_PCR9 */
PORT_HAL_SetMuxMode(PORTC_BASE,9u,kPortPinDisabled);
/* PORTE_PCR24 */
PORT_HAL_SetMuxMode(PORTE_BASE,24u,kPortPinDisabled);
/* PORTE_PCR25 */
PORT_HAL_SetMuxMode(PORTE_BASE,25u,kPortPinDisabled);
/* PORTC_PCR10 */
PORT_HAL_SetMuxMode(PORTC_BASE,10u,kPortPinDisabled);
/* PORTC_PCR11 */
PORT_HAL_SetMuxMode(PORTC_BASE,11u,kPortPinDisabled);
/* PORTC_PCR8 */
PORT_HAL_SetMuxMode(PORTC_BASE,8u,kPortPinDisabled);
/* PORTC_PCR5 */
PORT_HAL_SetMuxMode(PORTC_BASE,5u,kPortPinDisabled);
/* PORTB_PCR18 */
PORT_HAL_SetMuxMode(PORTB_BASE,18u,kPortPinDisabled);
/* PORTB_PCR19 */
PORT_HAL_SetMuxMode(PORTB_BASE,19u,kPortPinDisabled);
/* PORTC_PCR1 */
PORT_HAL_SetMuxMode(PORTC_BASE,1u,kPortPinDisabled);
/* PORTE_PCR26 */
PORT_HAL_SetMuxMode(PORTE_BASE,26u,kPortPinDisabled);
/* PORTD_PCR0 */
PORT_HAL_SetMuxMode(PORTD_BASE,0u,kPortPinDisabled);
/* PORTD_PCR3 */
PORT_HAL_SetMuxMode(PORTD_BASE,3u,kPortPinDisabled);
/* PORTD_PCR1 */
PORT_HAL_SetMuxMode(PORTD_BASE,1u,kPortPinDisabled);
/* PORTD_PCR2 */
PORT_HAL_SetMuxMode(PORTD_BASE,2u,kPortPinDisabled);
/* PORTB_PCR10 */
PORT_HAL_SetMuxMode(PORTB_BASE,10u,kPortPinDisabled);
/* PORTB_PCR17 */
PORT_HAL_SetMuxMode(PORTB_BASE,17u,kPortPinDisabled);
/* PORTB_PCR11 */
PORT_HAL_SetMuxMode(PORTB_BASE,11u,kPortPinDisabled);
/* PORTB_PCR16 */
PORT_HAL_SetMuxMode(PORTB_BASE,16u,kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD_BASE,0u,kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTD_BASE,4u,kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTE_BASE,24u,kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTE_BASE,25u,kPortPinDisabled);
/* PORTD_PCR4 (D7 - Green) */
PORT_HAL_SetMuxMode(PORTD_BASE, 4u, kPortPinDisabled);
}
void configure_cmp_pins(uint32_t instance)
{
PORT_HAL_SetMuxMode(PORTC,6u,kPortPinDisabled);
PORT_HAL_SetMuxMode(PORTC,5u,kPortMuxAlt6);
}
void setup_debug_pins(port_mux_t mux)
{
PORT_HAL_SetMuxMode(PORTA, 0u, mux);
PORT_HAL_SetMuxMode(PORTA, 3u, mux);
}
