STATIC void pyb_sleep_flash_powerdown (void) {
uint32_t status;
// Enable clock for SSPI module
MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// Reset SSPI at PRCM level and wait for reset to complete
MAP_PRCMPeripheralReset(PRCM_SSPI);
while(!MAP_PRCMPeripheralStatusGet(PRCM_SSPI));
// Reset SSPI at module level
MAP_SPIReset(SSPI_BASE);
// Configure SSPI module
MAP_SPIConfigSetExpClk (SSPI_BASE, PRCMPeripheralClockGet(PRCM_SSPI),
20000000, SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVELOW |
SPI_WL_8));
// Enable SSPI module
MAP_SPIEnable(SSPI_BASE);
// Enable chip select for the spi flash.
MAP_SPICSEnable(SSPI_BASE);
// Wait for the spi flash
do {
// Send the status register read instruction and read back a dummy byte.
MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_READ_STATUS);
MAP_SPIDataGet(SSPI_BASE, &status);
// Write a dummy byte then read back the actual status.
MAP_SPIDataPut(SSPI_BASE, 0xFF);
MAP_SPIDataGet(SSPI_BASE, &status);
} while ((status & 0xFF) == SPIFLASH_STATUS_BUSY);
// Disable chip select for the spi flash.
MAP_SPICSDisable(SSPI_BASE);
// Start another CS enable sequence for Power down command.
MAP_SPICSEnable(SSPI_BASE);
// Send Deep Power Down command to spi flash
MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_DEEP_POWER_DOWN);
// Disable chip select for the spi flash.
MAP_SPICSDisable(SSPI_BASE);
}
void init_SD_card(void)
{
//
// Enable MMCHS
//
PRCMPeripheralClkEnable(PRCM_SDHOST, PRCM_RUN_MODE_CLK);
//
// Reset MMCHS
//
PRCMPeripheralReset(PRCM_SDHOST);
//
// Configure MMCHS
//
SDHostInit(SDHOST_BASE);
//
// Configure card clock
//
SDHostSetExpClk(SDHOST_BASE, PRCMPeripheralClockGet(PRCM_SDHOST), 15000000);
}
/*
* ======== CameraCC3200DMA_open ========
*/
Camera_Handle CameraCC3200DMA_open(Camera_Handle handle, Camera_Params *params)
{
uintptr_t key;
CameraCC3200DMA_Object *object = handle->object;
CameraCC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs;
unsigned long hSyncPolarityConfig;
unsigned long vSyncPolarityConfig;
unsigned long byteOrderConfig;
unsigned long interfaceSync;
unsigned long pixelClkConfig;
HwiP_Params hwiParams;
SemaphoreP_Params semParams;
/* If params are NULL use defaults. */
if (params == NULL) {
params = (Camera_Params *) &Camera_defaultParams;
}
/* Timeouts cannot be 0 */
DebugP_assert((params->captureTimeout != 0));
/* Check that a callback is set */
DebugP_assert((params->captureMode != Camera_MODE_CALLBACK) ||
(params->captureCallback != NULL));
/* Disable preemption while checking if the Camera is open. */
key = HwiP_disable();
/* Check if the Camera is open already with the base addr. */
if (object->opened == true) {
HwiP_restore(key);
DebugP_log1("Camera:(%p) already in use.", hwAttrs->baseAddr);
return (NULL);
}
object->opened = true;
HwiP_restore(key);
object->operationMode = params->captureMode;
object->captureCallback = params->captureCallback;
object->captureTimeout = params->captureTimeout;
/* Set Camera variables to defaults. */
object->captureBuf = NULL;
object->bufferlength = 0;
object->frameLength = 0;
object->inUse = 0;
/*
* Register power dependency. Keeps the clock running in SLP
* and DSLP modes.
*/
Power_setDependency(PowerCC3200_PERIPH_CAMERA);
Power_setDependency(PowerCC3200_PERIPH_UDMA);
/* Disable the Camera interrupt. */
MAP_CameraIntDisable(hwAttrs->baseAddr, (CAM_INT_FE | CAM_INT_DMA));
HwiP_clearInterrupt(hwAttrs->intNum);
/* Create Hwi object for the Camera peripheral. */
/* Register the interrupt for this Camera peripheral. */
HwiP_Params_init(&hwiParams);
hwiParams.arg = (uintptr_t)handle;
hwiParams.priority = hwAttrs->intPriority;
object->hwiHandle = HwiP_create(hwAttrs->intNum, CameraCC3200DMA_hwiIntFxn,
&hwiParams);
if (object->hwiHandle == NULL) {
CameraCC3200DMA_close(handle);
return (NULL);
}
MAP_IntEnable(INT_CAMERA);
SemaphoreP_Params_init(&semParams);
semParams.mode = SemaphoreP_Mode_BINARY;
/* If capture is blocking create a semaphore and set callback. */
if (object->operationMode == Camera_MODE_BLOCKING) {
object->captureSem = SemaphoreP_create(0, &semParams);
if (object->captureSem) {
CameraCC3200DMA_close(handle);
return (NULL);
}
object->captureCallback = &captureSemCallback;
}
MAP_CameraReset(hwAttrs->baseAddr);
if (params->hsyncPolarity == Camera_HSYNC_POLARITY_HIGH) {
hSyncPolarityConfig = CAM_HS_POL_HI;
}
else {
hSyncPolarityConfig = CAM_HS_POL_LO;
}
if (params->vsyncPolarity == Camera_VSYNC_POLARITY_HIGH) {
vSyncPolarityConfig = CAM_VS_POL_HI;
}
else {
vSyncPolarityConfig = CAM_VS_POL_LO;
}
if (params->byteOrder == Camera_BYTE_ORDER_SWAP) {
byteOrderConfig = CAM_ORDERCAM_SWAP;
}
else {
byteOrderConfig = 0;
}
if (params->interfaceSync == Camera_INTERFACE_SYNC_OFF) {
interfaceSync = CAM_NOBT_SYNCHRO;
}
else {
interfaceSync = CAM_NOBT_SYNCHRO | CAM_IF_SYNCHRO | CAM_BT_CORRECT_EN;
}
if (params->pixelClkConfig == Camera_PCLK_CONFIG_RISING_EDGE) {
pixelClkConfig = CAM_PCLK_RISE_EDGE;
}
else {
pixelClkConfig = CAM_PCLK_FALL_EDGE;
}
MAP_CameraParamsConfig(hwAttrs->baseAddr, hSyncPolarityConfig,
vSyncPolarityConfig,
byteOrderConfig | interfaceSync | pixelClkConfig);
/*Set the clock divider based on the output clock */
MAP_CameraXClkConfig(hwAttrs->baseAddr,
PRCMPeripheralClockGet(PRCM_CAMERA),
params->outputClock);
/*Setting the FIFO threshold for a DMA request */
MAP_CameraThresholdSet(hwAttrs->baseAddr, 8);
MAP_CameraIntEnable(hwAttrs->baseAddr, (CAM_INT_FE | CAM_INT_DMA));
MAP_CameraDMAEnable(hwAttrs->baseAddr);
DebugP_log1("Camera:(%p) opened", hwAttrs->baseAddr);
/* Return the handle */
return (handle);
}
/*!
\brief open spi communication port to be used for communicating with a SimpleLink device
Given an interface name and option flags, this function opens the spi communication port
and creates a file descriptor. This file descriptor can be used afterwards to read and
write data from and to this specific spi channel.
The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
set to hardcoded values in this function.
\param ifName - points to the interface name/path. The interface name is an
optional attributes that the simple link driver receives
on opening the device. in systems that the spi channel is
not implemented as part of the os device drivers, this
parameter could be NULL.
\param flags - option flags
\return upon successful completion, the function shall open the spi channel and return
a non-negative integer representing the file descriptor.
Otherwise, -1 shall be returned
\sa spi_Close , spi_Read , spi_Write
\note
\warning
*/
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
SPICSDisable(ulBase);
//Disable SPI Channel
SPIDisable(ulBase);
// Reset SPI
SPIReset(ulBase);
//
// Configure SPI interface
//
SPIConfigSetExpClk(ulBase,PRCMPeripheralClockGet(PRCM_LSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
//g_ucDout[0]=0xFF;
//Simplelink_UDMAInit();
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
SPIFIFOEnable(ulBase,SPI_RX_FIFO);
SPIFIFOEnable(ulBase,SPI_TX_FIFO);
SPIDmaEnable(ulBase,SPI_RX_DMA);
SPIDmaEnable(ulBase,SPI_TX_DMA);
SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
IntEnable(INT_LSPI);
SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
/*
* ======== SPICC3200DMA_open ========
* @pre Function assumes that the handle is not NULL
*/
SPI_Handle SPICC3200DMA_open(SPI_Handle handle, SPI_Params *params)
{
uintptr_t key;
SPICC3200DMA_Object *object = handle->object;
SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs;
SemaphoreP_Params semParams;
HwiP_Params hwiParams;
key = HwiP_disable();
if(object->isOpen == true) {
HwiP_restore(key);
return (NULL);
}
object->isOpen = true;
HwiP_restore(key);
if (params == NULL) {
params = (SPI_Params *) &SPI_defaultParams;
}
DebugP_assert((params->dataSize >= 4) && (params->dataSize <= 32));
/* Determine if we need to use an 8, 16 or 32-bit frameSize for the DMA */
if (params->dataSize <= 8) {
object->frameSize = SPICC3200DMA_8bit;
}
else if (params->dataSize <= 16) {
object->frameSize = SPICC3200DMA_16bit;
}
else {
object->frameSize = SPICC3200DMA_32bit;
}
/* Store SPI mode of operation */
object->spiMode = params->mode;
object->transferMode = params->transferMode;
object->transaction = NULL;
object->rxFifoTrigger = (1 << object->frameSize);
object->txFifoTrigger = (1 << object->frameSize);
object->bitRate = params->bitRate;
object->frameFormat = params->frameFormat;
object->dataSize = params->dataSize;
/* Register power dependency - i.e. power up and enable clock for SPI. */
Power_setDependency(getPowerMgrId(hwAttrs->baseAddr));
Power_setDependency(PowerCC3200_PERIPH_UDMA);
Power_registerNotify(&(object->notifyObj), PowerCC3200_AWAKE_LPDS,
SPICC3200DMA_postNotify, (uintptr_t)handle);
HwiP_Params_init(&hwiParams);
hwiParams.arg = (uintptr_t)handle;
hwiParams.priority = hwAttrs->intPriority;
object->hwiHandle = HwiP_create(hwAttrs->intNum,
SPICC3200DMA_hwiFxn,
&hwiParams);
if (object->hwiHandle == NULL) {
SPICC3200DMA_close(handle);
return (NULL);
}
if (object->transferMode == SPI_MODE_BLOCKING) {
DebugP_log1("SPI:(%p) in SPI_MODE_BLOCKING mode", hwAttrs->baseAddr);
SemaphoreP_Params_init(&semParams);
semParams.mode = SemaphoreP_Mode_BINARY;
object->transferComplete = SemaphoreP_create(0, &semParams);
if (object->transferComplete == NULL) {
SPICC3200DMA_close(handle);
return (NULL);
}
object->transferCallbackFxn = SPICC3200DMA_transferCallback;
}
else {
DebugP_log1("SPI:(%p) in SPI_MODE_CALLBACK mode", hwAttrs->baseAddr);
DebugP_assert(params->transferCallbackFxn != NULL);
object->transferCallbackFxn = params->transferCallbackFxn;
}
if (uDMAControlBase == NULL) {
uDMAControlBase = MAP_uDMAControlBaseGet();
}
SPICC3200DMA_initHw(handle);
DebugP_log3("SPI:(%p) CPU freq: %d; SPI freq to %d",
hwAttrs->baseAddr, PRCMPeripheralClockGet(hwAttrs->spiPRCM),
params->bitRate);
DebugP_log1("SPI:(%p) opened", hwAttrs->baseAddr);
return (handle);
}
