void powerEnableSPIdomain(void){
// power on GPIO (CS und andere Pins sind GPIO PIns)
powerEnablePeriph();
powerEnableGPIOClockRunMode();
while((PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON));
PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL); // power on in MCU power domain -> prcm.cS
uint32_t debug = HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & PRCM_SSICLKGR_CLK_EN_SSI0; // enable clock for SSI
HWREG(PRCM_BASE + PRCM_O_SSICLKGR) = 1;
}
void radio_init(void) {
#if !RADIO_POLLED_MODE
// route all IRQs to CPE0
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) = 0;
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) = CPE0_MASK;
// clear any pending
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0;
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0;
//NVIC_EnableIRQ(rfc_cpe_0_IRQn);
//NVIC_EnableIRQ(rfc_cpe_1_IRQn);
NVIC_EnableIRQ(rfc_cmd_ack_IRQn);
#endif
// Power RF domain
PRCMPowerDomainOn(PRCM_DOMAIN_RFCORE);
while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE) != PRCM_DOMAIN_POWER_ON) ;
dprintf(INFO, "power on\n");
// enable the RF top clock
PRCMDomainEnable(PRCM_DOMAIN_RFCORE);
PRCMLoadSet();
dprintf(INFO, "top clock on\n");
// enable all RF sub clocks
RFCClockEnable();
dprintf(INFO, "clocks on\n");
thread_sleep(1000);
rf_patch_cpe_genfsk();
dprintf(INFO, "patched\n");
unsigned n = radio_send_cmd(IMM_CMD(CMD_PING, 0, 0));
dprintf(INFO, "RESPONSE %08x\n", n);
n = radio_send_cmd(IMM_CMD(CMD_PING, 0, 0));
dprintf(INFO, "RESPONSE %08x\n", n);
rf_op_fw_info_t fwinfo;
memset(&fwinfo, 0, sizeof(fwinfo));
fwinfo.cmd = CMD_GET_FW_INFO;
n = radio_send_cmd((uint32_t) &fwinfo);
dprintf(INFO, "FW %d %04x %04x %04x %04x\n",
n, fwinfo.version, fwinfo.free_ram_start,
fwinfo.free_ram_size, fwinfo.avail_rat_ch);
n = radio_send_cmd(IMM_CMD(CMD_START_RAT, 0, 0));
dprintf(INFO, "START RAT %d\n", n);
}
void timer_init(void){
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
PRCMLoadSet();
PRCMPeripheralSleepEnable(PRCM_PERIPH_TIMER2);
PRCMLoadSet();
PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_TIMER2);
PRCMLoadSet();
PRCMPeripheralRunEnable(PRCM_PERIPH_TIMER2);
PRCMLoadSet();
TimerDisable(GPT2_BASE, TIMER_BOTH);
TimerConfigure(GPT2_BASE, TIMER_CFG_PERIODIC);
TimerLoadSet(GPT2_BASE, TIMER_A, 48000000);
TimerIntClear(GPT2_BASE, TIMER_TIMA_TIMEOUT);
TimerIntEnable(GPT2_BASE, TIMER_TIMA_TIMEOUT);
TimerEnable(GPT2_BASE, TIMER_A);
}
Void Timer_enableCC26xx(Int id)
#endif
{
UInt gpt = INVALID_TIMER_ID;
/* map timer ID to the appropriate driverlib ID */
switch (id) {
case 0: gpt = PRCM_PERIPH_TIMER0;
break;
case 1: gpt = PRCM_PERIPH_TIMER1;
break;
case 2: gpt = PRCM_PERIPH_TIMER2;
break;
case 3: gpt = PRCM_PERIPH_TIMER3;
break;
default:
break;
}
/* if a valid GPT timer ID, enable the GPT ... */
if (gpt != INVALID_TIMER_ID) {
/* if it is not already on, turn on the PERIPH domain */
if (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) !=
PRCM_DOMAIN_POWER_ON) {
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) !=
PRCM_DOMAIN_POWER_ON) {};
}
/* now enable the GPT clocks */
PRCMPeripheralRunEnable(gpt);
PRCMPeripheralSleepEnable(gpt);
PRCMPeripheralDeepSleepEnable(gpt);
PRCMLoadSet();
while(!PRCMLoadGet()){};
}
}
/**
* Function documented in platform/uart.h
*/
otError otPlatUartEnable(void)
{
PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL);
while (PRCMPowerDomainStatus(PRCM_DOMAIN_SERIAL) != PRCM_DOMAIN_POWER_ON);
PRCMPeripheralRunEnable(PRCM_PERIPH_UART0);
PRCMPeripheralSleepEnable(PRCM_PERIPH_UART0);
PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_UART0);
PRCMLoadSet();
while (!PRCMLoadGet());
IOCPinTypeUart(UART0_BASE, IOID_2, IOID_3, IOID_UNUSED, IOID_UNUSED);
UARTConfigSetExpClk(UART0_BASE, SysCtrlClockGet(), 115200,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE);
UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTIntRegister(UART0_BASE, UART0_intHandler);
UARTEnable(UART0_BASE);
return OT_ERROR_NONE;
}
/*
* ======== Power_sleep ========
*/
Power_Status Power_sleep(Power_SleepState sleepState, UArg arg0, UArg arg1)
{
Power_Status status = Power_SOK;
UInt xosc_hf_active = FALSE;
Power_Event postEventLate;
UInt32 poweredDomains = 0;
Bool exitNow = FALSE;
Power_Event preEvent;
Power_Event postEvent;
UInt32 constraints;
Bool retainCache = FALSE;
UInt32 modeVIMS;
UInt taskKey;
UInt swiKey;
UInt hwiKey;
/* first validate the sleep code */
if ( sleepState != Power_STANDBY) {
status = Power_EFAIL;
}
if (status == Power_SOK) {
/* make sure Power is not still busy with a previous transition */
hwiKey = Hwi_disable();
if (Power_module->state == Power_ACTIVE) {
/* set transition state to entering sleep */
Power_module->state = Power_ENTERING_SLEEP;
}
else {
exitNow = TRUE;
}
Hwi_restore(hwiKey);
if (exitNow == TRUE) {
status = Power_EBUSY;
}
else {
/* setup sleep vars */
if (sleepState == Power_STANDBY) {
preEvent = Power_ENTERING_STANDBY;
postEvent = Power_AWAKE_STANDBY;
postEventLate = Power_AWAKE_STANDBY_LATE;
}
/* disable Task scheduling; allow Swis and Hwis for notifications */
taskKey = Task_disable();
/* signal all clients registered for pre-sleep notification */
status = Power_notify(preEvent);
/* check for any error */
if (status != Power_SOK) {
Power_module->state = Power_ACTIVE;
Task_restore(taskKey); /* re-enable scheduler */
return (status);
}
/* now disable Swi scheduling */
swiKey = Swi_disable();
/* freeze the IOs on the boundary between MCU and AON */
AONIOCFreezeEnable();
/* if XOSC_HF is active, force it off */
if(OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) {
xosc_hf_active = TRUE;
ti_sysbios_family_arm_cc26xx_Power_XOSC_HF(DISABLE);
}
/* allow AUX to power down */
AONWUCAuxWakeupEvent(AONWUC_AUX_ALLOW_SLEEP);
/* make sure writes take effect */
SysCtrlAonSync();
/* invoke specific sequences to activate sleep states... */
if (sleepState == Power_STANDBY) {
/* query and save domain states before powering them off */
if (Power_getDependencyCount(DOMAIN_RFCORE)) {
poweredDomains |= PRCM_DOMAIN_RFCORE;
}
if (Power_getDependencyCount(DOMAIN_SERIAL)){
poweredDomains |= PRCM_DOMAIN_SERIAL;
}
if (Power_getDependencyCount(DOMAIN_PERIPH)) {
poweredDomains |= PRCM_DOMAIN_PERIPH;
}
/* gate running deep sleep clocks for Crypto and DMA */
if (Power_getDependencyCount(PERIPH_CRYPTO)) {
PRCMPeripheralDeepSleepDisable(
ti_sysbios_family_arm_cc26xx_Power_db[
PERIPH_CRYPTO].driverlibID);
}
if (Power_getDependencyCount(PERIPH_UDMA)) {
PRCMPeripheralDeepSleepDisable(
ti_sysbios_family_arm_cc26xx_Power_db[
PERIPH_UDMA].driverlibID);
}
/* make sure clock settings take effect */
PRCMLoadSet();
/* request power off of domains in the MCU voltage domain */
PRCMPowerDomainOff(poweredDomains | PRCM_DOMAIN_CPU);
/* request uLDO during standby */
PRCMMcuUldoConfigure(true);
/* query constraints to determine if cache should be retained */
constraints = Power_getConstraintInfo();
if ((constraints & Power_SB_VIMS_CACHE_RETAIN) != 0) {
retainCache = TRUE;
}
/* if don't want retention in standby, disable it now ... */
if (retainCache == FALSE) {
modeVIMS = VIMSModeGet(VIMS_BASE);
/* wait if invalidate in progress... */
while (modeVIMS == VIMS_MODE_CHANGING) {
modeVIMS = VIMSModeGet(VIMS_BASE);
}
PRCMCacheRetentionDisable();
VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF);
}
/* setup recharge parameters */
SysCtrlSetRechargeBeforePowerDown(XoscInHighPowerMode);
/* make sure all writes have taken effect */
SysCtrlAonSync();
/* invoke deep sleep to go to STANDBY */
PRCMDeepSleep();
/* if didn't retain cache in standby, re-enable retention now */
if (retainCache == FALSE) {
VIMSModeSet(VIMS_BASE, modeVIMS);
PRCMCacheRetentionEnable();
}
/* force power on of AUX to keep it on when system is not
* sleeping; this also counts as a write to the AON interface
* ensuring that a following sync of the AON interface will
* force an update of all registers
*/
AONWUCAuxWakeupEvent(AONWUC_AUX_WAKEUP);
while(!(AONWUCPowerStatusGet() & AONWUC_AUX_POWER_ON)) {};
/* if XOSC_HF was forced off above, initiate switch back */
if (xosc_hf_active == TRUE) {
ti_sysbios_family_arm_cc26xx_Power_XOSC_HF(ENABLE);
}
/* restore power domain states in effect before standby */
PRCMPowerDomainOn(poweredDomains);
while (PRCMPowerDomainStatus(poweredDomains) !=
PRCM_DOMAIN_POWER_ON){};
/* restore deep sleep clocks of Crypto and DMA */
if (Power_getDependencyCount(PERIPH_CRYPTO)) {
PRCMPeripheralDeepSleepEnable(
ti_sysbios_family_arm_cc26xx_Power_db[
PERIPH_CRYPTO].driverlibID);
}
if (Power_getDependencyCount(PERIPH_UDMA)) {
PRCMPeripheralDeepSleepEnable(
ti_sysbios_family_arm_cc26xx_Power_db[
PERIPH_UDMA].driverlibID);
}
/* make sure clock settings take effect */
PRCMLoadSet();
}
/* release request for uLDO */
PRCMMcuUldoConfigure(false);
/* set transition state to EXITING_SLEEP */
Power_module->state = Power_EXITING_SLEEP;
/*
* signal clients registered for early post-sleep notification;
* this should be used to initialize any timing critical or IO
* dependent hardware
*/
status = Power_notify(postEvent);
/* disable IO freeze and ensure RTC shadow value is updated */
AONIOCFreezeDisable();
SysCtrlAonSync();
/* re-enable interrupts */
CPUcpsie();
/* signal all clients registered for late post-sleep notification */
status = Power_notify(postEventLate);
/* now clear the transition state before re-enabling scheduler */
Power_module->state = Power_ACTIVE;
/* re-enable Swi scheduling */
Swi_restore(swiKey);
/* adjust recharge parameters */
SysCtrlAdjustRechargeAfterPowerDown();
/* re-enable Task scheduling */
Task_restore(taskKey);
/* check for any notification error */
if (status != Power_SOK) {
return (status);
}
}
}
return (status);
}
/*
* ======== Power_setDependency ========
* Declare a dependency upon a resource.
*/
Bool Power_setDependency(Power_Resource resourceID)
{
UInt8 parent;
UInt8 count;
UInt32 id;
UInt key;
/* disable interrupts */
key = Hwi_disable();
/* read and increment reference count */
count = ti_sysbios_family_arm_cc26xx_Power_refCount[resourceID]++;
/* if resource was NOT activated previously ... */
if (count == 0) {
/* propagate set up the dependency tree ... */
/* check for a first parent */
parent = ti_sysbios_family_arm_cc26xx_Power_db[resourceID].flags
& PARENTMASK;
/* if first parent, make recursive call to set that dependency */
if (parent != NOPARENT) {
Power_setDependency(parent);
}
/* check for a second parent */
parent = ti_sysbios_family_arm_cc26xx_Power_db[resourceID].flags2
& PARENTMASK;
/* if second parent, make recursive call to set that dependency */
if (parent != NOPARENT) {
Power_setDependency(parent);
}
/* now activate this resource ... */
id = ti_sysbios_family_arm_cc26xx_Power_db[resourceID].driverlibID;
/* is resource a peripheral?... */
if (ti_sysbios_family_arm_cc26xx_Power_db[resourceID].flags & PERIPH) {
PRCMPeripheralRunEnable(id);
PRCMPeripheralSleepEnable(id);
PRCMPeripheralDeepSleepEnable(id);
PRCMLoadSet();
while(!PRCMLoadGet()){};
}
/* else, does resource require a special handler?... */
else if (ti_sysbios_family_arm_cc26xx_Power_db[resourceID].flags
& SPECIAL) {
/* call the special handler */
ti_sysbios_family_arm_cc26xx_Power_resourceHandlers[id](ENABLE);
}
/* else resource is a power domain */
else {
PRCMPowerDomainOn(id);
while (PRCMPowerDomainStatus(id) != PRCM_DOMAIN_POWER_ON) {};
}
}
/* re-enable interrupts */
Hwi_restore(key);
/* return the resource's activation status */
return (ti_sysbios_family_arm_cc26xx_Power_isDependencyActive(resourceID));
}