void HRPWM4_Config(period)
{
PWM_setPeriodLoad(myPwm4, PWM_PeriodLoad_Immediate);
PWM_setPeriod(myPwm4, period-1); // Set timer period
PWM_setCmpA(myPwm4, period / 2);
PWM_setCmpAHr(myPwm4, (1 << 8));
PWM_setCmpB(myPwm4, period / 2);
PWM_setPhase(myPwm4, 0x0000); // Phase is 0
PWM_setCount(myPwm4, 0x0000); // Clear counter
PWM_setCounterMode(myPwm4, PWM_CounterMode_Up); // Count up
PWM_disableCounterLoad(myPwm4); // Disable phase loading
PWM_setSyncMode(myPwm4, PWM_SyncMode_Disable);
PWM_setHighSpeedClkDiv(myPwm4, PWM_HspClkDiv_by_1); // Clock ratio to SYSCLKOUT
PWM_setClkDiv(myPwm4, PWM_ClkDiv_by_1);
PWM_setShadowMode_CmpA(myPwm4, PWM_ShadowMode_Shadow); // Load registers every ZERO
PWM_setShadowMode_CmpB(myPwm4, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm4, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm4, PWM_LoadMode_Zero);
PWM_setActionQual_Zero_PwmA(myPwm4, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm4, PWM_ActionQual_Clear);
PWM_setActionQual_Zero_PwmB(myPwm4, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpB_PwmB(myPwm4, PWM_ActionQual_Clear);
PWM_setHrEdgeMode(myPwm4, PWM_HrEdgeMode_Falling);
PWM_setHrControlMode(myPwm4, PWM_HrControlMode_Duty);
PWM_setHrShadowMode(myPwm4, PWM_HrShadowMode_CTR_EQ_0);
}
void InitEPwm1Example()
{
CLK_enablePwmClock(myClk, PWM_Number_1);
PWM_setPeriod(myPwm1, 6000); // Set timer period
PWM_setPhase(myPwm1, 0x0000); // Phase is 0
PWM_setCount(myPwm1, 0x0000);
// Setup TBCLK
PWM_setCounterMode(myPwm1, PWM_CounterMode_UpDown); // Count up/down
PWM_disableCounterLoad(myPwm1); // Disable phase loading
PWM_setHighSpeedClkDiv(myPwm1, PWM_HspClkDiv_by_4); // Clock ratio to SYSCLKOUT
PWM_setClkDiv(myPwm1, PWM_ClkDiv_by_4);
PWM_setShadowMode_CmpA(myPwm1, PWM_ShadowMode_Shadow); // Load registers every ZERO
PWM_setShadowMode_CmpB(myPwm1, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm1, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm1, PWM_LoadMode_Zero);
// Setup compare
PWM_setCmpA(myPwm1, 3000);
// Set actions
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm1, PWM_ActionQual_Set);
PWM_setActionQual_CntDown_CmpA_PwmA(myPwm1, PWM_ActionQual_Clear);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm1, PWM_ActionQual_Clear);
PWM_setActionQual_CntDown_CmpA_PwmB(myPwm1, PWM_ActionQual_Set);
// Define an event (DCAEVT1) based on TZ1 and TZ2
PWM_setDigitalCompareInput(myPwm1, PWM_DigitalCompare_A_High, PWM_DigitalCompare_InputSel_COMP1OUT); // DCAH = Comparator 1 output
PWM_setDigitalCompareInput(myPwm1, PWM_DigitalCompare_A_Low, PWM_DigitalCompare_InputSel_TZ2); // DCAL = TZ2
PWM_setTripZoneDCEventSelect_DCAEVT1(myPwm1, PWM_TripZoneDCEventSel_DCxHL_DCxLX); // DCAEVT1 = DCAH low(will become active as Comparator output goes low)
PWM_setDigitalCompareAEvent1(myPwm1, false, true, false, false); // DCAEVT1 = DCAEVT1 (not filtered), Take async path
// Define an event (DCBEVT1) based on TZ1 and TZ2
PWM_setDigitalCompareInput(myPwm1, PWM_DigitalCompare_B_High, PWM_DigitalCompare_InputSel_COMP1OUT); // DCBH = Comparator 1 output
PWM_setDigitalCompareInput(myPwm1, PWM_DigitalCompare_B_Low, PWM_DigitalCompare_InputSel_TZ2); // DCAL = TZ2
PWM_setTripZoneDCEventSelect_DCBEVT1(myPwm1, PWM_TripZoneDCEventSel_DCxHL_DCxLX); // DCBEVT1 = (will become active as Comparator output goes low)
PWM_setDigitalCompareBEvent1(myPwm1, false, true, false, false); // DCBEVT1 = DCBEVT1 (not filtered), Take async path
// Enable DCAEVT1 and DCBEVT1 are one shot trip sources
// Note: DCxEVT1 events can be defined as one-shot.
// DCxEVT2 events can be defined as cycle-by-cycle.
PWM_enableTripZoneSrc(myPwm1, PWM_TripZoneSrc_OneShot_CmpA);
PWM_enableTripZoneSrc(myPwm1, PWM_TripZoneSrc_OneShot_CmpB);
// What do we want the DCAEVT1 and DCBEVT1 events to do?
// DCAEVTx events can force EPWMxA
// DCBEVTx events can force EPWMxB
PWM_setTripZoneState_TZA(myPwm1, PWM_TripZoneState_EPWM_High); // EPWM1A will go high
PWM_setTripZoneState_TZB(myPwm1, PWM_TripZoneState_EPWM_Low); // EPWM1B will go low
// Enable TZ interrupt
PWM_enableTripZoneInt(myPwm1, PWM_TripZoneFlag_OST);
}
void InitEPwm2Example()
{
CLK_enablePwmClock(myClk, PWM_Number_2);
// Setup TBCLK
PWM_setCounterMode(myPwm2, PWM_CounterMode_Up); // Count up
PWM_setPeriod(myPwm2, EPWM2_TIMER_TBPRD); // Set timer period
PWM_disableCounterLoad(myPwm2); // Disable phase loading
PWM_setPhase(myPwm2, 0x0000); // Phase is 0
PWM_setCount(myPwm2, 0x0000); // Clear counter
PWM_setHighSpeedClkDiv(myPwm2, PWM_HspClkDiv_by_2); // Clock ratio to SYSCLKOUT
PWM_setClkDiv(myPwm2, PWM_ClkDiv_by_2);
// Setup shadow register load on ZERO
PWM_setShadowMode_CmpA(myPwm2, PWM_ShadowMode_Shadow);
PWM_setShadowMode_CmpB(myPwm2, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm2, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm2, PWM_LoadMode_Zero);
// Set Compare values
PWM_setCmpA(myPwm2, EPWM2_MIN_CMPA); // Set compare A value
PWM_setCmpB(myPwm2, EPWM2_MIN_CMPB); // Set Compare B value
// Set actions
PWM_setActionQual_Period_PwmA(myPwm2, PWM_ActionQual_Clear); // Clear PWM2A on Period
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm2, PWM_ActionQual_Set); // Set PWM2A on event A, up count
PWM_setActionQual_Period_PwmB(myPwm2, PWM_ActionQual_Clear); // Clear PWM2B on Period
PWM_setActionQual_CntUp_CmpB_PwmB(myPwm2, PWM_ActionQual_Set); // Set PWM2B on event B, up count
// Interrupt where we will change the Compare Values
PWM_setIntMode(myPwm2, PWM_IntMode_CounterEqualZero); // Select INT on Zero event
PWM_enableInt(myPwm2); // Enable INT
PWM_setIntPeriod(myPwm2, PWM_IntPeriod_ThirdEvent); // Generate INT on 3rd event
// Information this example uses to keep track
// of the direction the CMPA/CMPB values are
// moving, the min and max allowed values and
// a pointer to the correct ePWM registers
epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA
epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB
epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
epwm2_info.myPwmHandle = myPwm2; // Set the pointer to the ePWM module
epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values
epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA;
epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB;
epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB;
}
void HRPWM_Config(PWM_Handle myPwm, uint16_t period)
{
//Uint16 j;
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edge
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
// EDIS;
// for (j=1;j<PWM_CH;j++)
// {
// (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
// (*ePWM[j]).TBPRD = period-1; // PWM frequency = 1 / period
// (*ePWM[j]).CMPA.half.CMPA = period / 2; // set duty 50% initially
// (*ePWM[j]).CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
// (*ePWM[j]).CMPB = period / 2; // set duty 50% initially (edge 3 cycles after CTR=0)
// (*ePWM[j]).TBPHS.all = 0;
// (*ePWM[j]).TBCTR = 0;
PWM_setPeriodLoad(myPwm, PWM_PeriodLoad_Shadow);
PWM_setPeriod(myPwm, period-1); // Set timer period
PWM_setCmpA(myPwm, period / 2);
PWM_setCmpAHr(myPwm, (1 << 8));
PWM_setCmpB(myPwm, period / 2);
PWM_setPhase(myPwm, 0x0000); // Phase is 0
PWM_setCount(myPwm, 0x0000); // Clear counter
// (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UP; // Select up-count mode
// (*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE;
// (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
// (*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
// (*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
// (*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;
PWM_setCounterMode(myPwm, PWM_CounterMode_Up); // Count up
PWM_disableCounterLoad(myPwm); // Disable phase loading
PWM_setSyncMode(myPwm, PWM_SyncMode_Disable);
PWM_setHighSpeedClkDiv(myPwm, PWM_HspClkDiv_by_1); // Clock ratio to SYSCLKOUT
PWM_setClkDiv(myPwm, PWM_ClkDiv_by_1);
PWM_setRunMode(myPwm, PWM_RunMode_FreeRun);
// (*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // Load CMPA on CTR = PRD
// (*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
// (*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
// (*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
PWM_setShadowMode_CmpA(myPwm, PWM_ShadowMode_Shadow); // Load registers every ZERO
PWM_setShadowMode_CmpB(myPwm, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm, PWM_LoadMode_Zero);
// (*ePWM[j]).AQCTLA.bit.PRD = AQ_SET; // PWM toggle high/low
// (*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR;
// (*ePWM[j]).AQCTLB.bit.PRD = AQ_SET;
// (*ePWM[j]).AQCTLB.bit.CAU = AQ_CLEAR;
PWM_setActionQual_Period_PwmA(myPwm, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm, PWM_ActionQual_Clear);
PWM_setActionQual_Period_PwmB(myPwm, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm, PWM_ActionQual_Clear);
// EALLOW;
// (*ePWM[j]).HRCNFG.all = 0x0;
// (*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
// (*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
// (*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
//
// (*ePWM[j]).HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion
//
// (*ePWM[j]).HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
// EDIS;
PWM_setHrEdgeMode(myPwm, PWM_HrEdgeMode_Both);
PWM_setHrControlMode(myPwm, PWM_HrControlMode_Duty);
PWM_setHrShadowMode(myPwm, PWM_HrShadowMode_CTR_EQ_0_OR_PRD); // Enable auto-conversion logic
PWM_enableAutoConvert(myPwm);
PWM_enableHrPeriod(myPwm);
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the EPWM
// EDIS;
// (*ePWM[j]).TBCTL.bit.SWFSYNC = 1; // Sync for high resolution period
PWM_forceSync(myPwm);
// }
}
void HRPWM_Config(period)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edge
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
// EDIS;
// EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
// EPwm1Regs.TBPRD = period; // PWM frequency = 1/(2*TBPRD)
// EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
// EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
// EPwm1Regs.CMPB = period / 2; // set duty 50% initially
// EPwm1Regs.TBPHS.all = 0;
// EPwm1Regs.TBCTR = 0;
PWM_setPeriodLoad(myPwm1, PWM_PeriodLoad_Shadow);
PWM_setPeriod(myPwm1, period); // Set timer period
PWM_setCmpA(myPwm1, period / 2);
PWM_setCmpAHr(myPwm1, (1 << 8));
PWM_setCmpB(myPwm1, period / 2);
PWM_setPhase(myPwm1, 0x0000); // Phase is 0
PWM_setCount(myPwm1, 0x0000); // Clear counter
// EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down count mode
// EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // TBCTR phase load on SYNC (required for updown count HR control
// EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
// EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
// EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
// EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;
PWM_setCounterMode(myPwm1, PWM_CounterMode_UpDown); // Count up
PWM_enableCounterLoad(myPwm1); // Disable phase loading
PWM_setSyncMode(myPwm1, PWM_SyncMode_Disable);
PWM_setHighSpeedClkDiv(myPwm1, PWM_HspClkDiv_by_1); // Clock ratio to SYSCLKOUT
PWM_setClkDiv(myPwm1, PWM_ClkDiv_by_1);
PWM_setRunMode(myPwm1, PWM_RunMode_FreeRun);
// EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = 0
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
PWM_setShadowMode_CmpA(myPwm1, PWM_ShadowMode_Shadow); // Load registers every ZERO
PWM_setShadowMode_CmpB(myPwm1, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm1, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm1, PWM_LoadMode_Zero);
// EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // PWM toggle high/low
// EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // PWM toggle high/low
// EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
PWM_setActionQual_CntDown_CmpA_PwmA(myPwm1, PWM_ActionQual_Clear);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm1, PWM_ActionQual_Set);
PWM_setActionQual_CntDown_CmpA_PwmB(myPwm1, PWM_ActionQual_Clear);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm1, PWM_ActionQual_Set);
// EALLOW;
// EPwm1Regs.HRCNFG.all = 0x0;
// EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
// EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
// EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
// EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
//
// EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync (required for updwn count HR control)
// EPwm1Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
PWM_setHrEdgeMode(myPwm1, PWM_HrEdgeMode_Both);
PWM_setHrControlMode(myPwm1, PWM_HrControlMode_Duty);
PWM_setHrShadowMode(myPwm1, PWM_HrShadowMode_CTR_EQ_0_OR_PRD); // Enable auto-conversion logic
PWM_enableAutoConvert(myPwm1);
PWM_enableHrPhaseSync(myPwm1);
PWM_enableHrPeriod(myPwm1);
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the EPWM
// EPwm1Regs.TBCTL.bit.SWFSYNC = 1; // Synchronize high resolution phase to start HR period
// EDIS;
}
void InitEPwmTimer()
{
CLK_disableTbClockSync(myClk);
CLK_enablePwmClock(myClk, PWM_Number_1);
CLK_enablePwmClock(myClk, PWM_Number_2);
CLK_enablePwmClock(myClk, PWM_Number_3);
GPIO_setPullUp(myGpio, GPIO_Number_0, GPIO_PullUp_Disable);
GPIO_setPullUp(myGpio, GPIO_Number_1, GPIO_PullUp_Disable);
GPIO_setMode(myGpio, GPIO_Number_0, GPIO_0_Mode_EPWM1A);
GPIO_setMode(myGpio, GPIO_Number_1, GPIO_1_Mode_EPWM1B);
GPIO_setPullUp(myGpio, GPIO_Number_2, GPIO_PullUp_Disable);
GPIO_setPullUp(myGpio, GPIO_Number_3, GPIO_PullUp_Disable);
GPIO_setMode(myGpio, GPIO_Number_2, GPIO_2_Mode_EPWM2A);
GPIO_setMode(myGpio, GPIO_Number_3, GPIO_3_Mode_EPWM2B);
GPIO_setPullUp(myGpio, GPIO_Number_4, GPIO_PullUp_Disable);
GPIO_setPullUp(myGpio, GPIO_Number_5, GPIO_PullUp_Disable);
GPIO_setMode(myGpio, GPIO_Number_4, GPIO_4_Mode_EPWM3A);
GPIO_setMode(myGpio, GPIO_Number_5, GPIO_5_Mode_EPWM3B);
// Setup Sync
PWM_setSyncMode(myPwm1, PWM_SyncMode_EPWMxSYNC);
PWM_setSyncMode(myPwm2, PWM_SyncMode_EPWMxSYNC);
PWM_setSyncMode(myPwm3, PWM_SyncMode_EPWMxSYNC);
// Allow each timer to be sync'ed
PWM_enableCounterLoad(myPwm1);
PWM_enableCounterLoad(myPwm2);
PWM_enableCounterLoad(myPwm3);
// Set the phase
PWM_setPhase(myPwm1, 100);
PWM_setPhase(myPwm1, 200);
PWM_setPhase(myPwm1, 300);
PWM_setPeriod(myPwm1, PWM1_TIMER_TBPRD);
PWM_setCounterMode(myPwm1, PWM_CounterMode_Up); // Count up
PWM_setIntMode(myPwm1, PWM_IntMode_CounterEqualZero); // Select INT on Zero event
PWM_enableInt(myPwm1); // Enable INT
PWM_setIntPeriod(myPwm1, PWM_IntPeriod_FirstEvent); // Generate INT on 1st event
PWM_setPeriod(myPwm2, PWM2_TIMER_TBPRD);
PWM_setCounterMode(myPwm2, PWM_CounterMode_Up); // Count up
PWM_setIntMode(myPwm2, PWM_IntMode_CounterEqualZero); // Enable INT on Zero event
PWM_enableInt(myPwm2); // Enable INT
PWM_setIntPeriod(myPwm2, PWM_IntPeriod_SecondEvent); // Generate INT on 2nd event
PWM_setPeriod(myPwm3, PWM3_TIMER_TBPRD);
PWM_setCounterMode(myPwm3, PWM_CounterMode_Up); // Count up
PWM_setIntMode(myPwm3, PWM_IntMode_CounterEqualZero); // Enable INT on Zero event
PWM_enableInt(myPwm3); // Enable INT
PWM_setIntPeriod(myPwm3, PWM_IntPeriod_ThirdEvent); // Generate INT on 3rd event
PWM_setCmpA(myPwm1, PWM1_TIMER_TBPRD / 2);
PWM_setActionQual_Period_PwmA(myPwm1, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm1, PWM_ActionQual_Clear);
PWM_setActionQual_Period_PwmB(myPwm1, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm1, PWM_ActionQual_Clear);
PWM_setCmpA(myPwm2, PWM2_TIMER_TBPRD / 2);
PWM_setActionQual_Period_PwmA(myPwm2, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm2, PWM_ActionQual_Clear);
PWM_setActionQual_Period_PwmB(myPwm2, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm2, PWM_ActionQual_Clear);
PWM_setCmpA(myPwm3, PWM3_TIMER_TBPRD / 2);
PWM_setActionQual_Period_PwmA(myPwm3, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm3, PWM_ActionQual_Clear);
PWM_setActionQual_Period_PwmB(myPwm3, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpA_PwmB(myPwm3, PWM_ActionQual_Clear);
CLK_enableTbClockSync(myClk);
}