UINT32
PcieLanesToPowerDownPllInL1 (
IN UINT8 PllPowerUpLatency,
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LaneGroupExitLatency [4];
UINT32 LaneBitmapForPllOffInL1;
PCIe_ENGINE_CONFIG *EngineList;
UINTN Index;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n");
LaneBitmapForPllOffInL1 = 0;
if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) {
if (Wrapper->Features.PllOffInL1 != 0) {
LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie));
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
PCIe_ASPM_LATENCY_INFO LinkLatencyInfo;
UINT32 ActiveLanesBitmap;
UINT32 HotplugLanesBitmap;
if (EngineList->EngineData.EngineType == PciePortEngine) {
LinkLatencyInfo.MaxL1ExitLatency = 0;
LinkLatencyInfo.MaxL0sExitLatency = 0;
ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList);
HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList);
if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) {
PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
}
if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) {
LinkLatencyInfo.MaxL1ExitLatency = 0xff;
}
IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap);
for (Index = 0; Index < 4; Index++) {
if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) {
if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
}
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
LaneBitmapForPllOffInL1 = 0;
for (Index = 0; Index < 4; Index++) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
}
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n");
return LaneBitmapForPllOffInL1;
}
UINT32
PcieUtilGetWrapperLaneBitMap (
IN UINT32 IncludeLaneType,
IN UINT32 ExcludeLaneType,
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 LaneBitmap;
EngineList = PcieConfigGetChildEngine (Wrapper);
LaneBitmap = 0;
if ((IncludeLaneType | ExcludeLaneType) != 0) {
if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1;
if (ExcludeLaneType != 0) {
LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper));
}
} else {
while (EngineList != NULL) {
LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList);
EngineList = PcieLibGetNextDescriptor (EngineList);
}
if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper);
}
if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper));
}
}
}
return LaneBitmap;
}
BOOLEAN
PcieTopologyIsGen3SupportedV5 (
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
UINT8 LaneNibbleArray [4];
UINT32 LaneBitmap;
UINT8 Nibble;
UINT8 NibbleBitmap;
PCIe_ENGINE_CONFIG *Engine;
LibAmdMemFill (&LaneNibbleArray[0], 0x00, sizeof (LaneNibbleArray), PcieConfigGetStdHeader (Wrapper));
Engine = PcieConfigGetChildEngine (Wrapper);
while (Engine != NULL) {
LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Engine);
for (Nibble = 0; Nibble < 4; Nibble++) {
NibbleBitmap = (0xF << (Nibble * 4));
if ((LaneBitmap & NibbleBitmap) != 0) {
if (++LaneNibbleArray [Nibble] > 1) {
return FALSE;
}
}
}
Engine = PcieLibGetNextDescriptor (Engine);
}
return TRUE;
}
VOID
STATIC
PcieTopologyApplyLaneMuxCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Index;
UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
LibAmdMemCopy (
&TxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
LibAmdMemCopy (
&RxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
UINT32 CoreLaneBitmap;
UINT32 PifLaneBitmap;
UINT8 CurrentCoreLane;
UINT8 CurrentPifLane;
CoreLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, EngineList);
PifLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList);
IDS_HDT_CONSOLE (GNB_TRACE, "CoreLaneBitmap - %x, CurrentPifLane - %x\n", CoreLaneBitmap, PifLaneBitmap);
while (CoreLaneBitmap != 0) {
CurrentCoreLane = LibAmdBitScanForward (CoreLaneBitmap);
CurrentPifLane = LibAmdBitScanForward (PifLaneBitmap);
if (TxLaneMuxSelectorArray[CurrentPifLane] != CurrentCoreLane) {
TxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (TxLaneMuxSelectorArray, CurrentCoreLane)] = TxLaneMuxSelectorArray[CurrentPifLane];
TxLaneMuxSelectorArray[CurrentPifLane] = CurrentCoreLane;
}
if (RxLaneMuxSelectorArray[CurrentCoreLane] != CurrentPifLane) {
RxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (RxLaneMuxSelectorArray, CurrentPifLane)] = RxLaneMuxSelectorArray[CurrentCoreLane];
RxLaneMuxSelectorArray[CurrentCoreLane] = CurrentPifLane;
}
CoreLaneBitmap &= (~ (1 << CurrentCoreLane));
PifLaneBitmap &= (~ (1 << CurrentPifLane));
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
for (Index = 0; Index < 2; ++Index) {
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0121_ADDRESS + Index),
((UINT32 *) TxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0125_ADDRESS + Index),
((UINT32 *) RxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Exit\n");
}
