unsigned long get_board_ddr_clk(void) { u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT /* use accurate clock measurement */ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); u32 val; val = freq * base; if (val) { debug("DDR Clock measurement is: %d\n", val); return val; } else { printf("Warning: DDR clock measurement is invalid, "); printf("using value from brdcfg1.\n"); } #endif switch ((ddrclk_conf & 0x30) >> 4) { case QIXIS_DDRCLK_100: return 100000000; case QIXIS_DDRCLK_125: return 125000000; case QIXIS_DDRCLK_133: return 133333333; } return 66666666; }
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) { u32 pixel_format; u8 sw; /*Route I2C4 to DIU system as HSYNC/VSYNC*/ sw = QIXIS_READ(brdcfg[5]); QIXIS_WRITE(brdcfg[5], ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); /*Configure Display ouput port as HDMI*/ sw = QIXIS_READ(brdcfg[15]); QIXIS_WRITE(brdcfg[15], ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); return fsl_diu_init(xres, yres, pixel_format, 0); }
int checkboard(void) { u8 sw; sw = QIXIS_READ(arch); printf("Board: %s, ", CONFIG_IDENT_STRING); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); puts("\nSERDES2 Reference : "); printf("Clock1 = 100MHz "); printf("Clock2 = 100MHz\n"); return 0; }
void qixis_dump_switch(void) { int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); nr_of_cfgsw = QIXIS_READ(cms[1]); puts("DIP switch settings dump:\n"); for (i = 1; i <= nr_of_cfgsw; i++) { QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } }
int checkboard(void) { #ifdef CONFIG_TFABOOT enum boot_src src = get_boot_src(); #endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; #endif puts("Board: LS1043AQDS, boot from "); #ifdef CONFIG_TFABOOT if (src == BOOT_SOURCE_SD_MMC) puts("SD\n"); else { #endif #ifdef CONFIG_SD_BOOT puts("SD\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); else if (sw == 0xF) printf("QSPI\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif #ifdef CONFIG_TFABOOT } #endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); return 0; }
int esdhc_status_fixup(void *blob, const char *compat) { char esdhc0_path[] = "/soc/esdhc@1560000"; char esdhc1_path[] = "/soc/esdhc@1580000"; u8 card_id; do_fixup_by_path(blob, esdhc0_path, "status", "okay", sizeof("okay"), 1); /* * The Presence Detect 2 register detects the installation * of cards in various PCI Express or SGMII slots. * * STAT_PRS2[7:5]: Specifies the type of card installed in the * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. */ card_id = (QIXIS_READ(present2) & 0xe0) >> 5; /* If no adapter is installed in SDHC2, disable SDHC2 */ if (card_id == 0x7) do_fixup_by_path(blob, esdhc1_path, "status", "disabled", sizeof("disabled"), 1); else do_fixup_by_path(blob, esdhc1_path, "status", "okay", sizeof("okay"), 1); return 0; }
int board_early_init_f(void) { #ifdef CONFIG_HAS_FSL_XHCI_USB struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif #ifdef CONFIG_LPUART u8 uart; #endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); #endif fsl_lsch2_early_init_f(); #ifdef CONFIG_HAS_FSL_XHCI_USB out_be32(&scfg->rcwpmuxcr0, 0x3333); out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); uart &= ~CFG_UART_MUX_MASK; uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; QIXIS_WRITE(brdcfg[14], uart); #endif return 0; }
static void ls1021a_mux_mdio(int addr) { u8 brdcfg4; brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= EMI1_MASK; switch (addr) { case EMI1_RGMII0: brdcfg4 |= 0; break; case EMI1_RGMII1: brdcfg4 |= 0x20; break; case EMI1_RGMII2: brdcfg4 |= 0x40; break; case EMI1_SGMII1: brdcfg4 |= 0x60; break; case EMI1_SGMII2: brdcfg4 |= 0x80; break; default: brdcfg4 |= 0xa0; break; } QIXIS_WRITE(brdcfg[4], brdcfg4); }
int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; u8 reg; /* fixup DT for the two DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif reg = QIXIS_READ(brdcfg[0]); reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; /* Disable IFC if QSPI is enabled */ if (reg == 0xF) do_fixup_by_compat(blob, "fsl,ifc", "status", "disabled", 8 + 1, 1); return 0; }
unsigned long get_board_sys_clk(void) { u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0f) { case QIXIS_SYSCLK_64: return 64000000; case QIXIS_SYSCLK_83: return 83333333; case QIXIS_SYSCLK_100: return 100000000; case QIXIS_SYSCLK_125: return 125000000; case QIXIS_SYSCLK_133: return 133333333; case QIXIS_SYSCLK_150: return 150000000; case QIXIS_SYSCLK_160: return 160000000; case QIXIS_SYSCLK_166: return 166666666; } return 66666666; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); set_liodns(); #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; }
static void set_brdcfg9_for_gtx_clk(void) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); brdcfg9 |= (1 << 5); QIXIS_WRITE(brdcfg[9], brdcfg9); }
int config_board_mux(int ctrl_type) { u8 reg12, reg14; reg12 = QIXIS_READ(brdcfg[12]); reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { case MUX_TYPE_CAN: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); break; case MUX_TYPE_IIC2: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); break; case MUX_TYPE_RGMII: reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); break; case MUX_TYPE_SAI: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); break; case MUX_TYPE_SDHC: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_SD_PCI4: reg12 = 0x38; break; case MUX_TYPE_SD_PC_SA_SG_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SA_PC_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SG_SG: reg12 = 0x21; break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[12], reg12); QIXIS_WRITE(brdcfg[14], reg14); return 0; }
int checkboard(void) { char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; static const char *freq[4] = { "100.00MHZ(from 8T49N222A)", "125.00MHz", "156.25MHZ", "100.00MHz" }; printf("Board: %sQDS, ", cpu->name); sw = QIXIS_READ(arch); printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); #ifdef CONFIG_SDCARD puts("SD/MMC\n"); #elif CONFIG_SPIFLASH puts("SPI\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank%d\n", sw); else if (sw == 0x8) puts("Promjet\n"); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); puts("SERDES Reference Clocks:\n"); sw = QIXIS_READ(brdcfg[2]); printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], freq[(sw >> 4) & 0x3]); printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], freq[sw & 0x3]); return 0; }
/* Set the boot bank to the alternate bank */ void set_altbank(void) { u8 reg; reg = QIXIS_READ(brdcfg[0]); reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; QIXIS_WRITE(brdcfg[0], reg); }
static void ls2080a_qds_enable_SFP_TX(u8 muxval) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); brdcfg9 &= ~BRDCFG9_SFPTX_MASK; brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); QIXIS_WRITE(brdcfg[9], brdcfg9); }
static void set_brdcfg9_for_gtx_clk(void) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); /* Initializing EPHY2 clock to RGMII mode */ brdcfg9 &= ~(BRDCFG9_EPHY2_MASK); brdcfg9 |= (BRDCFG9_EPHY2_VAL); QIXIS_WRITE(brdcfg[9], brdcfg9); }
static void t1040_qds_mux_mdio(u8 muxval) { u8 brdcfg4; if (muxval <= 7) { brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= ~BRDCFG4_EMISEL_MASK; brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); QIXIS_WRITE(brdcfg[4], brdcfg4); } }
int checkboard(void) { #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) char buf[64]; #endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif puts("Board: LS1021AQDS\n"); #ifdef CONFIG_SD_BOOT puts("SD\n"); #elif CONFIG_QSPI_BOOT puts("QSPI\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); else if (sw == 0x15) printf("IFCCard\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); #endif return 0; }
unsigned long get_board_ddr_clk(void) { u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); switch ((ddrclk_conf & 0x30) >> 4) { case QIXIS_DDRCLK_100: return 100000000; case QIXIS_DDRCLK_125: return 125000000; case QIXIS_DDRCLK_133: return 133333333; } return 66666666; }
/* * Board rev C and earlier has duplicated I2C addresses for 2nd controller. * Both slots has 0x54, resulting 2nd slot unusable. */ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { u8 sw; sw = QIXIS_READ(arch); if ((sw & 0xf) < 0x3) { if (ctrl_num == 1 && slot == 0) *addr = SPD_EEPROM_ADDRESS4; else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } }
unsigned long get_board_sys_clk(void) { u8 sysclk_conf = QIXIS_READ(brdcfg[1]); #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT /* use accurate clock measurement */ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); u32 val; val = freq * base; if (val) { debug("SYS Clock measurement is: %d\n", val); return val; } else { printf("Warning: SYS clock measurement is invalid, "); printf("using value from brdcfg1.\n"); } #endif switch (sysclk_conf & 0x0F) { case QIXIS_SYSCLK_83: return 83333333; case QIXIS_SYSCLK_100: return 100000000; case QIXIS_SYSCLK_125: return 125000000; case QIXIS_SYSCLK_133: return 133333333; case QIXIS_SYSCLK_150: return 150000000; case QIXIS_SYSCLK_160: return 160000000; case QIXIS_SYSCLK_166: return 166666666; } return 66666666; }
int checkboard(void) { char buf[64]; u8 sw; sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); if (sw & QIXIS_LBMAP_ALTBANK) printf("flash: 2\n"); else printf("flash: 1\n"); printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); return 0; }
int board_early_init_f(void) { #ifdef CONFIG_LPUART u8 uart; #endif fsl_lsch2_early_init_f(); #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); uart &= ~CFG_UART_MUX_MASK; uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; QIXIS_WRITE(brdcfg[14], uart); #endif return 0; }
int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; if (argc <= 1) { clear_altbank(); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { set_altbank(); qixis_bank_reset(); } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; u8 rcfg = QIXIS_READ(rcfg_ctl); if (argv[2] == NULL) { printf("qixis watchdog <watchdog_period>\n"); return 0; } for (i = 0; i < ARRAY_SIZE(period); i++) { if (strcmp(argv[2], period[i]) == 0) { /* disable watchdog */ QIXIS_WRITE(rcfg_ctl, rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); QIXIS_WRITE(watch, ((i<<2) - 1)); QIXIS_WRITE(rcfg_ctl, rcfg); return 0; } } } #ifdef DEBUG else if (strcmp(argv[1], "dump") == 0) { qixis_dump_regs(); return 0; } #endif else { printf("Invalid option: %s\n", argv[1]); return 1; } return 0; }
int config_board_mux(int ctrl_type) { u8 reg14; reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { case MUX_TYPE_GPIO: reg14 = (reg14 & (~0x6)) | 0x2; break; default: puts("Unsupported mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[14], reg14); return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); if (flash_esel == -1) { /* very unlikely unless something is messed up */ puts("Error: Could not find TLB for FLASH BASE\n"); flash_esel = 2; /* give our best effort to continue */ } else { /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. */ if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; }
int config_board_mux(int ctrl_type) { u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); switch (ctrl_type) { case MUX_TYPE_SDHC: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_DSPI: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[5], reg5); return 0; }
bool if_board_diff_clk(void) { u8 diff_conf = QIXIS_READ(brdcfg[11]); return diff_conf & 0x40; }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { case 0xd5: case 0xd6: /* QSGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, 0x8); fm_info_set_phy_address(FM1_DTSEC2, 0x9); fm_info_set_phy_address(FM1_DTSEC3, 0xa); fm_info_set_phy_address(FM1_DTSEC4, 0xb); break; case 0x95: case 0x99: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks the * XAUI card is used for the XFI MAC, which will cause error. */ fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6f: /* SGMII in Slot3, Slot4, Slot5 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x7f: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x47: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x77: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x5a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x5b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; default: break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); } if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII2; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII1; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC1 + idx); if (lane < 0) break; mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }