/* Reads a page from the EEPROM using combined IRQ I2C transfer. */
void i2c_irq_combined_transaction_example()
{
QM_PUTS("IRQ combined write + read");
async_irq_read_xfer.tx = eeprom_read_addr;
async_irq_read_xfer.tx_len = EEPROM_ADDR_SIZE_BYTES;
async_irq_read_xfer.callback = i2c_0_irq_callback;
async_irq_read_xfer.callback_data = &id_read;
async_irq_read_xfer.rx = eeprom_read_buf;
async_irq_read_xfer.rx_len = EEPROM_PAGE_SIZE_BYTES;
async_irq_read_xfer.stop = true;
i2c_0_irq_complete = false;
i2c_0_irq_rc_error = false;
if (qm_i2c_master_irq_transfer(QM_I2C_0, &async_irq_read_xfer,
EEPROM_SLAVE_ADDR)) {
QM_PUTS("Error: IRQ read failed");
}
/* Wait until complete flag is set in callback. */
while (!i2c_0_irq_complete)
;
if (i2c_0_irq_rc_error) {
QM_PUTS("Error: I2C IRQ Transfer failed");
} else {
QM_PUTS("I2C IRQ Transfer complete");
}
}
/* Writes a page to the EEPROM using IRQ I2C transfer. */
void i2c_irq_write_example()
{
QM_PUTS("IRQ write");
async_irq_write_xfer.tx = eeprom_irq_write_data;
async_irq_write_xfer.tx_len =
EEPROM_PAGE_SIZE_BYTES + EEPROM_ADDR_SIZE_BYTES;
async_irq_write_xfer.callback = i2c_0_irq_callback;
async_irq_write_xfer.callback_data = &id_write;
async_irq_write_xfer.rx = NULL;
async_irq_write_xfer.rx_len = 0;
async_irq_write_xfer.stop = true;
if (qm_i2c_master_irq_transfer(QM_I2C_0, &async_irq_write_xfer,
EEPROM_SLAVE_ADDR)) {
QM_PUTS("Error: IRQ write failed");
}
/* Wait until complete flag is set in callback. */
while (!i2c_0_irq_complete)
;
if (i2c_0_irq_rc_error) {
QM_PUTS("Error: I2C IRQ Transfer failed");
} else {
QM_PUTS("I2C IRQ Transfer complete");
}
/* Wait for EEPROM to complete the write operation. */
clk_sys_udelay(EEPROM_WRITE_WAIT_TIME_US);
}
int main(void)
{
qm_gpio_port_config_t cfg;
QM_PUTS("Starting: AON GPIO");
/* Request IRQ and write GPIO port config. */
cfg.direction = 0; /* Set all pins as inputs. */
cfg.int_en = BIT(PIN_INTR); /* Interrupt enabled. */
cfg.int_type = BIT(PIN_INTR); /* Edge sensitive interrupt. */
cfg.int_polarity = ~BIT(PIN_INTR); /* Falling edge. */
cfg.int_debounce = BIT(PIN_INTR); /* Debounce enabled. */
cfg.int_bothedge = 0; /* Both edge disabled. */
cfg.callback = aon_gpio_example_callback;
cfg.callback_data = NULL;
qm_irq_request(QM_IRQ_AON_GPIO_0_INT, qm_aon_gpio_0_isr);
qm_gpio_set_config(QM_AON_GPIO_0, &cfg);
QM_PUTS("AON GPIO set up, press 'PB0' to trigger the interrupt");
/* Wait for the AON GPIO callback to be invoked and print the status. */
while (!callback_invoked)
;
QM_PRINTF("Status of AON GPIO callback = 0x%u \n", callback_status);
QM_PUTS("Finished: AON GPIO");
return 0;
}
int main(void)
{
/* Comparator example app
*
* This app sets up comparator 0 to fire an interrupt when the input
* voltage is greater than the reference voltage (0.95V)
*
* On the Intel(R) Quark(TM) Microcontroller D2000 Development Platform
* the pin used is marked "SSO 10"
*/
qm_ac_config_t ac_cfg;
QM_PUTS("Analog Comparators example app start\n");
/* Set up pin muxing and request IRQ*/
qm_pmux_select(QM_PIN_ID_0, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_0, true);
qm_irq_request(QM_IRQ_AC, qm_ac_isr);
/* Write configs */
ac_cfg.reference = BIT(0); /* Ref internal voltage */
ac_cfg.polarity = 0x0; /* Fire if greater than ref (high level) */
ac_cfg.power = BIT(0); /* Normal operation mode */
ac_cfg.int_en = BIT(0); /* AIN0 enable */
ac_cfg.callback = ac_example_callback;
qm_ac_set_config(&ac_cfg);
QM_PUTS("Analog Comparators example app complete\n");
return 0;
}
/* Configures DMA. */
void i2c_dma_setup()
{
/* Request interrupts for the DMA controller. */
QM_IR_UNMASK_INT(QM_IRQ_DMA_0_INT_0);
QM_IR_UNMASK_INT(QM_IRQ_DMA_0_INT_1);
QM_IR_UNMASK_INT(QM_IRQ_DMA_0_ERROR_INT);
QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_0, qm_dma_0_isr_0);
QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_1, qm_dma_0_isr_1);
QM_IRQ_REQUEST(QM_IRQ_DMA_0_ERROR_INT, qm_dma_0_error_isr);
/* Init DMA controller. */
if (qm_dma_init(QM_DMA_0)) {
QM_PUTS("Error: DMAC init failed");
}
/* Configure the TX channel. */
if (qm_i2c_dma_channel_config(QM_I2C_0, QM_DMA_0, I2C_DMA_TX_CHANNEL_ID,
QM_DMA_MEMORY_TO_PERIPHERAL)) {
QM_PUTS("Error: TX channel configuring failed");
}
/* Configure the RX channel. */
if (qm_i2c_dma_channel_config(QM_I2C_0, QM_DMA_0, I2C_DMA_RX_CHANNEL_ID,
QM_DMA_PERIPHERAL_TO_MEMORY)) {
QM_PUTS("Error: Channel config failed");
}
}
/*
* Waits for the previous DMA TX transfer to finish and starts a combined
* transaction using the 2 channels previously configured.
*/
void i2c_dma_combined_transaction_example()
{
QM_PUTS("I2C DMA Combined transaction");
/* Set the ongoing TX and RX flags. */
dma_read_done = false;
dma_write_done = false;
dma_error = false;
/* Config the transfer. */
async_dma_combined_xfer.tx = eeprom_read_addr;
async_dma_combined_xfer.tx_len = EEPROM_ADDR_SIZE_BYTES;
async_dma_combined_xfer.rx = eeprom_read_buf;
async_dma_combined_xfer.rx_len = EEPROM_PAGE_SIZE_BYTES;
async_dma_combined_xfer.callback = i2c_user_dma_combined_trans_callback;
async_dma_combined_xfer.callback_data = NULL;
async_dma_combined_xfer.stop = true;
qm_i2c_master_dma_transfer(QM_I2C_0, &async_dma_combined_xfer,
EEPROM_SLAVE_ADDR);
/* Wait for the operation to finish. */
while ((!dma_write_done) || (!dma_read_done))
;
if (dma_error) {
QM_PUTS("Error: I2C DMA transfer failed");
} else {
QM_PUTS("I2C DMA Transfer complete");
}
}
/* Configures the DMA TX channel and starts a TX transfer. */
void i2c_dma_write_example()
{
QM_PUTS("I2C DMA TX");
/* Set the ongoing TX flag. */
dma_write_done = false;
dma_error = false;
/* Config the transfer. */
async_dma_write_xfer.tx = eeprom_pio_write_data;
async_dma_write_xfer.tx_len =
EEPROM_PAGE_SIZE_BYTES + EEPROM_ADDR_SIZE_BYTES;
async_dma_write_xfer.rx = NULL;
async_dma_write_xfer.rx_len = 0;
async_dma_write_xfer.callback = i2c_user_dma_write_callback;
async_dma_write_xfer.callback_data = NULL;
async_dma_write_xfer.stop = true;
/* Start TX */
qm_i2c_master_dma_transfer(QM_I2C_0, &async_dma_write_xfer,
EEPROM_SLAVE_ADDR);
/* Wait for the operation to finish. */
while (!dma_write_done)
;
if (dma_error) {
QM_PUTS("Error: I2C DMA transfer failed");
} else {
QM_PUTS("I2C DMA Transfer complete");
}
}
int main(void)
{
qm_i2c_config_t cfg;
QM_PUTS("Starting: I2C");
QM_IR_UNMASK_INT(QM_IRQ_I2C_0_INT);
QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_irq_isr);
/* Enable I2C 0. */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_I2C_M0_REGISTER);
pin_mux_setup();
/* Configure I2C. */
cfg.address_mode = QM_I2C_7_BIT;
cfg.mode = QM_I2C_MASTER;
cfg.speed = QM_I2C_SPEED_STD;
if (qm_i2c_set_config(QM_I2C_0, &cfg)) {
QM_PUTS("Error: I2C_0 config failed");
}
/* Add eeprom data address to the beginning of each message. */
eeprom_pio_write_data[0] = EEPROM_ADDR_FIRST_PAGE_LO;
eeprom_pio_write_data[1] = EEPROM_ADDR_FIRST_PAGE_HI;
eeprom_irq_write_data[0] = EEPROM_ADDR_FIRST_PAGE_LO;
eeprom_irq_write_data[1] = EEPROM_ADDR_FIRST_PAGE_HI;
/* PIO example. */
i2c_pio_write_example();
i2c_pio_combined_transaction_example();
eeprom_compare_page(eeprom_pio_write_data, eeprom_read_buf);
/* IRQ example. */
i2c_irq_write_example();
i2c_irq_combined_transaction_example();
eeprom_compare_page(eeprom_irq_write_data, eeprom_read_buf);
/* DMA example. */
/* Verify irq callback was fired before initiating a new request */
while (!i2c_0_irq_complete)
;
QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_dma_isr);
i2c_dma_setup();
i2c_dma_write_example();
i2c_dma_combined_transaction_example();
eeprom_compare_page(eeprom_pio_write_data, eeprom_read_buf);
QM_PUTS("Finished: I2C");
return 0;
}
int main(void)
{
qm_rtc_config_t rtc_cfg;
unsigned int count = 0;
/* loop_max : Maximum number of iterations.
* A value of 50 will run the application for roughly 30s.
*/
const unsigned int loop_max = 50;
gpio_init();
pin_mux_setup();
gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */
/* Clear Screen. */
QM_PUTS("Starting: Power Profiler");
QM_PUTS("Low power mode example.");
QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1));
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
/* Initialise RTC configuration: Run, but don't interrupt. */
rtc_cfg.init_val = 0;
rtc_cfg.alarm_en = 0;
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1);
rtc_cfg.callback = rtc_example_callback;
rtc_cfg.prescaler = CLK_RTC_DIV_1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
QM_IR_UNMASK_INT(QM_IRQ_RTC_0_INT);
QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
#if (!QM_SENSOR)
test_clock_rates();
#endif
/* Enable the RTC Interrupt. */
rtc_cfg.alarm_en = 1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
count = 0;
while (++count < loop_max) {
QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick);
slow_mode_test();
halt_test();
core_sleep_test();
/* TODO : Enable soc_sleep test for c1000. */
soc_sleep_test();
/* TODO : Enable soc_deep_sleep test for d2000 and c1000. */
soc_deep_sleep_test();
}
SOC_WATCH_TRIGGER_FLUSH();
QM_PUTS("Finished: Power Profiler");
return 0;
}
static void spi_transfer_irq(void)
{
QM_PUTS("Reading CHIPID in IRQ mode.");
tx_buffer[0] = 0x80; /* Read chip ID. */
/* Set up transfer values. */
qm_ss_spi_async_transfer_t irq_trans;
irq_trans.rx = rx_buffer;
irq_trans.tx = tx_buffer;
irq_trans.rx_len = BUFFER_SIZE;
irq_trans.tx_len = BUFFER_SIZE;
irq_trans.callback_data = NULL;
irq_trans.callback = spi_cb;
/* Register interrupts. */
qm_ss_irq_request(QM_SS_IRQ_SPI_0_ERROR_INT, qm_ss_spi_0_error_isr);
qm_ss_irq_request(QM_SS_IRQ_SPI_0_RX_AVAIL_INT,
qm_ss_spi_0_rx_avail_isr);
qm_ss_irq_request(QM_SS_IRQ_SPI_0_TX_REQ_INT, qm_ss_spi_0_tx_req_isr);
tx_buffer[0] = 0x80; /* Read chip ID. */
err_code = 0;
xfer_active = true;
/* Set SPI configuration. */
qm_ss_spi_set_config(spi, &conf);
/* Enable clock for SPI 0. */
ss_clk_spi_enable(QM_SS_SPI_0);
/* Select slave and do the actual SPI transfer. */
qm_ss_spi_slave_select(spi, select);
qm_ss_spi_irq_transfer(spi, &irq_trans);
while (xfer_active)
;
/* Disable clock for SPI 0. */
ss_clk_spi_disable(QM_SS_SPI_0);
if (err_code != 0) {
QM_PRINTF(
"Error: SPI transfer failed. (%d frames transmitted)\n",
transfer_len);
} else if (rx_buffer[1] == 0xd1) {
QM_PUTS("CHIPID = 0x1d");
} else {
QM_PRINTF("Error: CHIPID doesn't match 0x%x != 0xd1.\n",
rx_buffer[1]);
}
}
void spi_rx_example_cb(uint32_t id, uint32_t len)
{
int i;
QM_PUTS("\nSPI RX DONE\n");
/* Compare RX and TX buffers */
for (i = 0; i < BUFFERSIZE; i++) {
if (tx_buff[i] != rx_buff[i]) {
QM_PUTS("\nERROR: RX/TX Buffers mismatch!\n");
} else if (i == BUFFERSIZE - 1) {
QM_PUTS("\nSUCCESS: Buffers match!\n");
}
}
}
static void ss_gpio_interrupt_example(void)
{
uint32_t i;
QM_PUTS("Starting: SS GPIO interrupt");
/* Enable clock to interrupt controller. */
__builtin_arc_sr(BIT(31) + BIT(0),
QM_SS_GPIO_0_BASE + QM_SS_GPIO_LS_SYNC);
/* Set SS GPIO pin 2 as OUTPUT. */
__builtin_arc_sr(BIT(2), QM_SS_GPIO_0_BASE + QM_SS_GPIO_SWPORTA_DDR);
/* Register the SS GPIO interrupt. */
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask);
qm_ss_irq_request(QM_SS_IRQ_GPIO_0_INT, ss_gpio_interrupt_isr);
/* Set the bit 3 to rising edge-sensitive. */
__builtin_arc_sr(BIT(3), QM_SS_GPIO_0_BASE + QM_SS_GPIO_INTTYPE_LEVEL);
/* Unmask SS GPIO pin 3 interrupt only. */
__builtin_arc_sr(~BIT(3), QM_SS_GPIO_0_BASE + QM_SS_GPIO_INTMASK);
/* Clear SS GPIO interrupt requests. */
__builtin_arc_sr(BIT(3), QM_SS_GPIO_0_BASE + QM_SS_GPIO_PORTA_EOI);
/* Enable SS GPIO interrupt. */
__builtin_arc_sr(BIT(3), QM_SS_GPIO_0_BASE + QM_SS_GPIO_INTEN);
for (i = 0; i < NUM_LOOPS; i++) {
/*
* Toggle the SS GPIO 2, will trigger the interrupt on SS
* GPIO 3.
*/
clk_sys_udelay(DELAY);
__builtin_arc_sr(BIT(2),
QM_SS_GPIO_0_BASE + QM_SS_GPIO_SWPORTA_DR);
QM_GPIO[0]->gpio_swporta_dr |= BIT(LED_BIT);
clk_sys_udelay(DELAY);
__builtin_arc_sr(0, QM_SS_GPIO_0_BASE + QM_SS_GPIO_SWPORTA_DR);
QM_GPIO[0]->gpio_swporta_dr &= ~BIT(LED_BIT);
}
/* Unmask all SS GPIO interrupts. */
__builtin_arc_sr(0xff, QM_SS_GPIO_0_BASE + QM_SS_GPIO_INTMASK);
if (counter == NUM_LOOPS) {
QM_PUTS("Success");
} else {
QM_PUTS("Error: Check are pins 14 and 16 on J14 connector "
"short connected?");
}
QM_PUTS("Finished: SS GPIO interrupt");
}
int main(void)
{
qm_ss_gpio_state_t state;
qm_ss_gpio_port_config_t conf;
QM_PUTS("Starting: SS GPIO");
pin_mux_setup();
/* Request IRQ and write SS GPIO port config. */
conf.direction = BIT(PIN_OUT); /* Set PIN_OUT to output. */
conf.int_en = BIT(PIN_INTR); /* Interrupt enabled. */
conf.int_type = BIT(PIN_INTR); /* Edge sensitive interrupt. */
conf.int_polarity = ~BIT(PIN_INTR); /* Falling edge. */
conf.int_debounce = BIT(PIN_INTR); /* Debounce enabled. */
conf.callback = gpio_example_callback;
conf.callback_data = NULL;
/* Enable clock. */
ss_clk_gpio_enable(QM_SS_GPIO_0);
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask);
qm_ss_irq_request(QM_SS_IRQ_GPIO_0_INT, qm_ss_gpio_0_isr);
qm_ss_gpio_set_config(QM_SS_GPIO_0, &conf);
/* Clear PIN_OUT to trigger PIN_INTR interrupt. */
qm_ss_gpio_set_pin(QM_SS_GPIO_0, PIN_OUT);
qm_ss_gpio_clear_pin(QM_SS_GPIO_0, PIN_OUT);
/* Wait for callback to be invoked */
while (!callback_invoked)
;
QM_PRINTF("Callback fired, status: 0x%x\n", callback_status);
if (qm_ss_gpio_read_pin(QM_SS_GPIO_0, PIN_OUT, &state)) {
QM_PUTS("Error: read pin failed");
return 1;
}
if (state != QM_SS_GPIO_LOW) {
QM_PUTS("Error: SS GPIO pin out comparison failed");
return 1;
}
QM_PUTS("Finished: SS GPIO");
return 0;
}
int main(void)
{
qm_flash_config_t cfg;
uint32_t wr_flash_addr, app_end, page_num, flash_base, flash_num;
#if (QUARK_D2000)
flash_base = QM_FLASH_REGION_SYS_0_BASE;
flash_num = QM_FLASH_0;
#elif(QUARK_SE)
flash_base = QM_FLASH_REGION_SYS_1_BASE;
flash_num = QM_FLASH_1;
#endif
QM_PUTS("Starting: Flash");
app_end = (uint32_t)__data_lma + (uint32_t)__data_size;
/* Check there is at least one free flash page after the app code. */
if ((app_end + QM_FLASH_PAGE_SIZE_BYTES) > FLASH_END) {
QM_PUTS("Error: No free pages. Quitting.");
return 1;
}
/*
* Calculate flash page number, and an MMIO address representing a
* location inside the page.
*/
page_num = ((app_end - flash_base) / QM_FLASH_PAGE_SIZE_BYTES) + 1;
wr_flash_addr = (QM_FLASH_PAGE_SIZE_BYTES * page_num) + WR_PAGE_OFFSET;
cfg.us_count = US_COUNT;
cfg.wait_states = WAIT_STATES;
cfg.write_disable = QM_FLASH_WRITE_ENABLE;
qm_flash_set_config(flash_num, &cfg);
/* Requires a 2KB buffer to store flash page. */
qm_flash_page_update(flash_num, QM_FLASH_REGION_SYS, wr_flash_addr,
flash_page_buffer, flash_data, NUM_DATA_WORDS);
qm_flash_page_erase(flash_num, QM_FLASH_REGION_SYS, page_num);
qm_flash_page_write(flash_num, QM_FLASH_REGION_SYS, page_num,
flash_data, NUM_DATA_WORDS);
QM_PUTS("Finished: Flash");
return 0;
}
int main(void)
{
qm_mpr_config_t cfg;
uint8_t lower_bound;
uint32_t heap_offset, mpr_base;
QM_PUTS("Starting: MPR");
/*
* The MPR is located in the heap in order to ensure it doesn't clash
* with anything so it is necessary to calculate the page number that
* corresponds to the start of the heap.
*/
heap_offset = (uint32_t)&__heap;
lower_bound = (uint8_t)((heap_offset - SRAM_BASE) / MPR_PAGE_SIZE) + 1;
/* Calculate the physical address of the start of the MPR. */
mpr_base = SRAM_BASE + (lower_bound * MPR_PAGE_SIZE);
/* Request the IRQ. */
qm_irq_request(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);
/* Set the violation policy to trigger an interrupt. */
qm_mpr_set_violation_policy(MPR_VIOL_MODE_INTERRUPT,
mpr_example_callback, NULL);
/* Configure MPR to allow R/W from DMA agent only. */
cfg.en_lock_mask = QM_SRAM_MPR_EN_MASK_ENABLE;
cfg.agent_read_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.agent_write_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.up_bound = lower_bound;
cfg.low_bound = lower_bound;
qm_mpr_set_config(QM_MPR_0, &cfg);
/* Trigger a violation event by attempting a write inside the MPR. */
REG_VAL(mpr_base + 1) = 0xff;
/* Wait for the callback to be invoked. */
while (false == callback_invoked)
;
QM_PUTS("MPR Violation!");
QM_PUTS("Finished: MPR");
return 0;
}
void uart_example_tx_callback(void *data, int error, qm_uart_status_t status,
uint32_t len)
{
uint32_t id = *(uint32_t *)data;
switch (id) {
case BANNER_IRQ_ID:
qm_uart_write_buffer(STDOUT_UART,
(uint8_t *)BANNER_IRQ_COMPLETE,
sizeof(BANNER_IRQ_COMPLETE));
break;
case BANNER_DMA_ID:
qm_uart_write_buffer(STDOUT_UART,
(uint8_t *)BANNER_DMA_COMPLETE,
sizeof(BANNER_DMA_COMPLETE));
break;
default:
break;
}
QM_PUTS("\n");
}
/* Writes a page to the EEPROM using PIO I2C transfer. */
void i2c_pio_write_example()
{
qm_i2c_status_t status;
QM_PUTS("PIO write");
/* Write EEPROM page address then the data. */
if (qm_i2c_master_write(QM_I2C_0, EEPROM_SLAVE_ADDR,
eeprom_pio_write_data,
sizeof(eeprom_pio_write_data), true, &status)) {
QM_PUTS("Error: PIO write failed");
} else {
QM_PUTS("I2C PIO TX Transfer complete");
}
clk_sys_udelay(EEPROM_WRITE_WAIT_TIME_US);
}
int main(void)
{
unsigned int cnt;
QM_PUTS("Demonstrating QM_PUTS/QM_PRINTF functionality");
for (cnt = 0; cnt < 10; cnt++) {
QM_PRINTF("%d\n", cnt);
}
QM_PUTS("Demonstrating QM_ASSERT functionality");
QM_ASSERT(1 == 0);
return 0;
}
int main(void)
{
uint32_t c_val = 0, pt_val = 0;
qm_aonpt_config_t cfg;
QM_PUTS("Starting: Always-on Counter");
/* Always-on Counter enable and read value. */
qm_aonc_enable(QM_AONC_0);
if (qm_aonc_get_value(QM_AONC_0, &c_val) == 0) {
QM_PRINTF("Always-on Counter value: %u\n", c_val);
} else {
QM_PUTS("Error: Could not read aonc value.");
}
/* Request an IRQ and write the Always-on Periodic Timer config. */
cfg.count = 0x1000; /* 0.125 seconds. */
cfg.int_en = true; /* Interrupts enabled. */
cfg.callback = aonpt_example_callback;
qm_irq_request(QM_IRQ_AONPT_0_INT, qm_aonpt_0_isr);
qm_aonpt_set_config(QM_AONC_0, &cfg);
/* Wait for the defined number of callbacks be invoked. */
while (NUM_CALLBACKS > callback_count)
;
QM_PRINTF("Periodic Timer callback fired %d times.\n", callback_count);
/* Get the value of the Always-on Periodic Timer. */
if (qm_aonpt_get_value(QM_AONC_0, &c_val) == 0) {
QM_PRINTF("Always-on Periodic Timer value: %u\n", pt_val);
} else {
QM_PUTS("Error: Could not read Periodic timer value");
}
/* Disable the always-on periodic timer interrupt. */
cfg.int_en = false;
qm_aonpt_set_config(QM_AONC_0, &cfg);
QM_PUTS("Finished: Always-on counter");
return 0;
}
int main(void)
{
qm_rtc_config_t rtc_cfg;
unsigned int count = 0;
/* Maximum number of 3-second iterations. */
const unsigned int loop_max = 5;
gpio_init();
gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */
/* Clear Screen. */
QM_PUTS("Starting: Power Profiler");
QM_PUTS("Low power mode example.");
QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1));
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
/* Initialise RTC configuration: Run, but don't interrupt. */
rtc_cfg.init_val = 0;
rtc_cfg.alarm_en = 0;
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1);
rtc_cfg.callback = rtc_example_callback;
rtc_cfg.prescaler = CLK_RTC_DIV_1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
qm_irq_request(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
test_clock_rates();
/* Enable the RTC Interrupt. */
rtc_cfg.alarm_en = 1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
count = 0;
while (++count < loop_max) {
QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick);
slow_mode_test();
halt_test();
sleep_test();
#if DEEP_SLEEP
deep_sleep_test();
#endif
}
QM_PUTS("Finished: Power Profiler");
return 0;
}
int main(void)
{
QM_PUTS("Starting: SS SPI");
/* Set up SPI configuration. */
conf.frame_size = QM_SS_SPI_FRAME_SIZE_8_BIT;
conf.transfer_mode = QM_SS_SPI_TMOD_TX_RX;
conf.clk_divider = 32; /* 1MHz. */
conf.bus_mode = QM_SS_SPI_BMODE_0;
spi_transfer_polled();
spi_transfer_irq();
QM_PUTS("Finished: SS SPI");
return 0;
}
static void soc_sleep_test(void)
{
#if SOC_SLEEP_TEST
/* Go to sleep, (power down some IO). RTC will wake me up. */
QM_PUTS("SOC Sleep");
ENTER_SOC_SLEEP();
#endif
}
static void halt_test(void)
{
#if HALT_TEST
/* Halt the CPU, RTC alarm will wake me up. */
QM_PUTS("Halt");
ENTER_C1();
#endif
}
int main(void)
{
uint32_t rom_version = qm_ver_rom();
QM_PUTS("Starting: Version");
QM_PRINTF("QMSI API version number (int) is %u\n", QM_VER_API_UINT);
QM_PRINTF("QMSI API version number (string) is %s\n",
QM_VER_API_STRING);
QM_PRINTF("QMSI ROM version number (int) is %u\n",
(unsigned int)rom_version);
QM_PUTS("Finished: Version");
return 0;
}
int main(void)
{
uint32_t baudrate, dtr = 0;
int bytes_read;
QM_PUTS("Starting: USB CDC ACM Example");
qm_irq_request(QM_IRQ_USB_0_INT, qm_usb_0_isr);
/* Enable the USB VBUS on Quark SE DevBoard. */
enable_usb_vbus();
/* Init USB CDC ACM. */
cdc_acm_init();
QM_PUTS("CDC ACM Initialized. Waiting for DTR.");
do {
cdc_acm_line_ctrl_get(LINE_CTRL_DTR, &dtr);
} while (!dtr);
QM_PUTS("DTR set, start test.");
/* Wait 1 sec for the host to do all settings. */
clk_sys_udelay(ONE_SEC_UDELAY);
if (cdc_acm_line_ctrl_get(LINE_CTRL_BAUD_RATE, &baudrate)) {
QM_PUTS("Failed to get baudrate, ret code.");
} else {
QM_PRINTF("Baudrate detected: %d\n", baudrate);
}
QM_PUTS("USB CDC ACM set. Switch to the USB Serial Console.");
cdc_acm_irq_callback_set(interrupt_handler);
write_data(banner1, strlen(banner1));
write_data(banner2, strlen(banner2));
/* Enable RX interrupts. */
cdc_acm_irq_rx_enable();
/* Echo the received data. */
while (1) {
read_and_echo_data(&bytes_read);
}
return 0;
}
int main(void)
{
volatile uint32_t delay;
uint32_t c_val = 0, pt_val = 0;
qm_aonpt_config_t cfg;
QM_PUTS("\nAlways-on Counter example app\n");
/* Always-on Counter enable, disable and read value */
qm_aonc_disable(QM_SCSS_AON_0);
qm_aonc_enable(QM_SCSS_AON_0);
c_val = qm_aonc_get_value(QM_SCSS_AON_0);
if (c_val) {
QM_PRINTF("Always-on Counter value: %lu\n", c_val);
} else {
QM_PRINTF("ERROR: Could not read aonc value\n");
}
/* Request an IRQ and write the Always-on Periodic Timer config */
cfg.count = 0x10000;
cfg.int_en = true;
cfg.callback = aonpt_example_callback;
qm_irq_request(QM_IRQ_AONPT_0, qm_aonpt_isr_0);
qm_aonpt_set_config(QM_SCSS_AON_0, &cfg);
/* The AON Periodic Timer runs from the RTC clock at 32KHz (rather than
* the system clock which is 32MHz) so we need to spin for a few cycles
* allow the register change to propagate */
for (delay = 500; delay--;) {
}
/* Get the value of the Always-on Periodic Timer */
pt_val = qm_aonpt_get_value(QM_SCSS_AON_0);
if (pt_val) {
QM_PRINTF("Always-on Periodic Timer value: %lu\n", pt_val);
} else {
QM_PRINTF("ERROR: Could not read Periodic timer value\n\n");
}
QM_PUTS("Always-on counter example app complete\n");
return 0;
}
void soc_sleep_requested(bool ready_to_sleep)
{
unsigned int key;
QM_PUTS("SoC sleep requested");
if (!ready_to_sleep) {
QM_PUTS("Sleep NAK'd");
send_msg(SLEEP_NAK);
} else {
key = qm_irq_lock();
send_msg(SLEEP_ACK);
soc_sleep(CORE_SLEEP);
qm_irq_unlock(key);
}
return;
}
static void core_sleep_test(void)
{
#if CORE_SLEEP_TEST
/* Halt the CPU, RTC alarm will wake me up. */
QM_PUTS("CPU C2");
#if (QM_SENSOR)
/* switch rtc interrupt to level triggered.*/
rtc_trigger = switch_rtc_to_level();
#endif
ENTER_CORE_SLEEP_1();
#if (QM_SENSOR)
/* restore rtc interrupt back to edge triggered.*/
restore_rtc_trigger(rtc_trigger);
#endif
QM_PUTS("CPU C2LP");
ENTER_CORE_SLEEP_2();
#endif
}
static void soc_deep_sleep_test(void)
{
#if SOC_DEEP_SLEEP_TEST
/* Go to sleep, (power down some IO). RTC will wake me up. */
QM_PUTS("SOC Deep Sleep");
/* TODO : save/restore context soc_deep_sleep test. */
ENTER_SOC_DEEP_SLEEP();
#endif
}
static void slow_mode_test(void)
{
#if SLOW_MODE_TEST
/* Drop into low-power compute mode. */
QM_PUTS("\nSlow");
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_8);
ENTER_HALT();
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1);
#endif
}
