/** ============================================================================
* @n@b Init_Qmss
*
* @b Description
* @n This API initializes the QMSS LLD.
*
* @param[in]
* @n None
*
* @return Int32
* -1 - Error
* 0 - Success
* =============================================================================
*/
Int32 Init_Qmss (Void)
{
Int32 result;
Qmss_MemRegInfo memCfg;
Qmss_MemRegInfo sriomemCfg;
Qmss_InitCfg qmssInitConfig;
Cppi_DescCfg cppiDescCfg;
UInt32 numAllocated;
/* Initialize QMSS */
memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
/* Set up QMSS configuration */
/* Use internal linking RAM */
qmssInitConfig.linkingRAM0Base = 0;
qmssInitConfig.linkingRAM0Size = 0;
qmssInitConfig.linkingRAM1Base = 0x0;
qmssInitConfig.maxDescNum = NUM_SRIO_HOST_DESC+NUM_CPSW_HOST_DESC;
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
#ifdef _LITTLE_ENDIAN
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);
#else
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);
#endif
/* Initialize the Queue Manager */
result = Qmss_init (&qmssInitConfig, qmssGblCfgParams);
if (result != QMSS_SOK)
{
uart_write ("Error initializing Queue Manager SubSystem, Error code : %d\n", result);
return -1;
}
/* Start Queue manager on this core */
Qmss_start ();
/* Setup the descriptor memory regions.
*
* The Descriptor base addresses MUST be global addresses and
* all memory regions MUST be setup in ascending order of the
* descriptor base addresses.
*/
/* Initialize and setup CPSW Host Descriptors required for example */
memset (gHostDesc, 0, SIZE_CPSW_HOST_DESC * NUM_CPSW_HOST_DESC);
memCfg.descBase = (UInt32 *) Convert_CoreLocal2GlobalAddr ((UInt32) gHostDesc);
memCfg.descSize = SIZE_CPSW_HOST_DESC;
memCfg.descNum = NUM_CPSW_HOST_DESC;
memCfg.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
memCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;
memCfg.startIndex = 0;
/* Insert Host Descriptor memory region */
result = Qmss_insertMemoryRegion(&memCfg);
if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
{
uart_write ("Memory Region %d already Initialized \n", memCfg.memRegion);
}
else if (result < QMSS_SOK)
{
uart_write ("Error: Inserting CPSW memory region %d, Error code : %d\n", memCfg.memRegion, result);
return -1;
}
else
uart_write ("Debug: Memory Region %d inserted :0x%x size of desc %d num of the desc %d\n",memCfg.memRegion,gHostDesc,SIZE_CPSW_HOST_DESC,NUM_CPSW_HOST_DESC);
/* Initialize and setup SRIO Host Descriptors required for example */
memset (host_region, 0, SIZE_SRIO_HOST_DESC * NUM_SRIO_HOST_DESC);
sriomemCfg.descBase = (UInt32 *) Convert_CoreLocal2GlobalAddr ((UInt32) host_region);
sriomemCfg.descSize = SIZE_SRIO_HOST_DESC;
sriomemCfg.descNum = NUM_SRIO_HOST_DESC;
sriomemCfg.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
sriomemCfg.memRegion = Qmss_MemRegion_MEMORY_REGION1;
sriomemCfg.startIndex = NUM_CPSW_HOST_DESC;
/* Insert Host Descriptor memory region */
result = Qmss_insertMemoryRegion(&sriomemCfg);
if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
{
uart_write ("Memory Region %d already Initialized \n", sriomemCfg.memRegion);
}
else if (result < QMSS_SOK)
{
uart_write ("Error: Inserting SRIO memory region %d, Error code : %d\n", sriomemCfg.memRegion, result);
return -1;
}
else
uart_write ("Debug:Memory Region %d inserted :0x%x size of desc %d num of the desc %d\n",sriomemCfg.memRegion,host_region,SIZE_SRIO_HOST_DESC,NUM_SRIO_HOST_DESC);
/* Initialize all the descriptors we just allocated on the
* memory region above. Setup the descriptors with some well
* known values before we use them for data transfers.
*/
memset (&cppiDescCfg, 0, sizeof (cppiDescCfg));
cppiDescCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;
cppiDescCfg.descNum = NUM_CPSW_HOST_DESC;
cppiDescCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;
cppiDescCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
cppiDescCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;
cppiDescCfg.descType = Cppi_DescType_HOST;
/* By default:
* (1) Return descriptors to tail of queue
* (2) Always return entire packet to this free queue
* (3) Set that PS Data is always present in start of SOP buffer
* (4) Configure free q num < 4K, hence qMgr = 0
* (5) Recycle back to the same Free queue by default.
*/
cppiDescCfg.returnPushPolicy = Qmss_Location_TAIL;
cppiDescCfg.cfg.host.returnPolicy = Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;
cppiDescCfg.cfg.host.psLocation = Cppi_PSLoc_PS_IN_DESC;
cppiDescCfg.returnQueue.qMgr = 0;
cppiDescCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;
cppiDescCfg.epibPresent = Cppi_EPIB_EPIB_PRESENT;
/* Initialize the descriptors, create a free queue and push descriptors to a global free queue */
if ((gGlobalFreeQHnd = Cppi_initDescriptor (&cppiDescCfg, &numAllocated)) <= 0)
{
uart_write ("Error Initializing Free Descriptors, Error: %d \n", gGlobalFreeQHnd);
return -1;
}
else
uart_write("No of descriptors in CPSW global free queue %d \n",Qmss_getQueueEntryCount(gGlobalFreeQHnd));
/* Queue Manager Initialization Done */
return 0;
}
/**
* Init Queue Manager SUbSystem (QMSS)
* - Configure QMSS Driver
* - Define Memory regions
* -
*/
void init_qmss(int useMsmc){
int i, result;
Qmss_InitCfg qmss_initCfg;
Cppi_CpDmaInitCfg cpdmaCfg;
Qmss_GlobalConfigParams qmss_globalCfg;
/* Descriptor base addresses */
void* data_desc_base = (void*)align((int)msmc_mem_base);
void* ctrl_desc_base = (void*)align((int)data_desc_base + DATA_DESC_NUM*DATA_DESC_SIZE);
void* trace_desc_base = (void*)align((int)ctrl_desc_base + CTRL_DESC_NUM*CTRL_DESC_SIZE);
void* fftc_desc_base = (void*)align((int)trace_desc_base + TRACE_DESC_NUM*TRACE_DESC_SIZE);
if(useMsmc){
data_mem_base = align((int)fftc_desc_base + FFTC_DESC_NUM*FFTC_DESC_SIZE);
}else{
data_mem_base = align((int)ddr_mem_base);
}
/* Initialize QMSS Driver */
memset (&qmss_initCfg, 0, sizeof (Qmss_InitCfg));
/* Use internal linking RAM */
qmss_initCfg.linkingRAM0Base = 0;
qmss_initCfg.linkingRAM0Size = 0;
qmss_initCfg.linkingRAM1Base = 0;
qmss_initCfg.maxDescNum = DATA_DESC_NUM + CTRL_DESC_NUM + TRACE_DESC_NUM + FFTC_DESC_NUM;
qmss_initCfg.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
qmss_initCfg.pdspFirmware[0].firmware = &acc48_le;
qmss_initCfg.pdspFirmware[0].size = sizeof (acc48_le);
/* Bypass hardware initialization as it is done within Kernel */
qmss_initCfg.qmssHwStatus = QMSS_HW_INIT_COMPLETE;
qmss_globalCfg = qmssGblCfgParams;
/* Convert address to Virtual address */
for(i=0;i < (int)qmss_globalCfg.maxQueMgrGroups;i++){
TranslateAddress(qmss_globalCfg.groupRegs[i].qmConfigReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_configRegs*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmDescReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_descriptor_region_configRegs*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_managementRegs*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtProxyReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_managementRegs*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueStatReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_queue_status_configRegs*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmStatusRAM, qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_Queue_Status*);
TranslateAddress(qmss_globalCfg.groupRegs[i].qmQueMgmtDataReg, qmss_cfg_regs-CSL_QMSS_DATA_BASE, CSL_Qm_queue_managementRegs*);
/* not supported on k2 hardware, and not used by lld */
qmss_globalCfg.groupRegs[i].qmQueMgmtProxyDataReg = 0;
}
for(i=0;i < QMSS_MAX_INTD;i++)
TranslateAddress(qmss_globalCfg.regs.qmQueIntdReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_Qm_intdRegs*);
for(i=0;i < QMSS_MAX_PDSP;i++){
TranslateAddress(qmss_globalCfg.regs.qmPdspCmdReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*);
TranslateAddress(qmss_globalCfg.regs.qmPdspCtrlReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, CSL_PdspRegs*);
TranslateAddress(qmss_globalCfg.regs.qmPdspIRamReg[i], qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*);
}
TranslateAddress(qmss_globalCfg.regs.qmLinkingRAMReg, qmss_cfg_regs-CSL_QMSS_CFG_BASE, volatile uint32_t*);
TranslateAddress(qmss_globalCfg.regs.qmBaseAddr, qmss_cfg_regs-CSL_QMSS_CFG_BASE, void*);
if ((result = Qmss_init (&qmss_initCfg, &qmss_globalCfg)) != QMSS_SOK){
printf ("initQmss: Error initializing Queue Manager SubSystem, Error code : %d\n", result);
abort();
}
if ((result = Qmss_start ()) != QMSS_SOK){
printf ("initQmss: Error starting Queue Manager SubSystem, Error code : %d\n", result);
abort();
}
Cppi_GlobalCPDMAConfigParams translatedCppiGblCpdmaCfgParams[Cppi_CpDma_LAST+1];
Cppi_GlobalConfigParams translatedCppiGblCfgParams = cppiGblCfgParams;
translatedCppiGblCfgParams.cpDmaCfgs = translatedCppiGblCpdmaCfgParams;
#define translateCpdma(reg, type) (translatedCppiGblCfgParams.reg = (type)(((int) cppiGblCfgParams.reg ) + cppi_regs - CPPI_BASE_REG))
Cppi_CpDma cpdma;
for(cpdma = Cppi_CpDma_SRIO_CPDMA; cpdma <= Cppi_CpDma_LAST; cpdma++){
translatedCppiGblCfgParams.cpDmaCfgs[cpdma] = cppiGblCfgParams.cpDmaCfgs[cpdma];
translateCpdma(cpDmaCfgs[cpdma].gblCfgRegs, CSL_Cppidma_global_configRegs*);
translateCpdma(cpDmaCfgs[cpdma].txChRegs, CSL_Cppidma_tx_channel_configRegs*);
translateCpdma(cpDmaCfgs[cpdma].rxChRegs, CSL_Cppidma_rx_channel_configRegs*);
translateCpdma(cpDmaCfgs[cpdma].txSchedRegs,CSL_Cppidma_tx_scheduler_configRegs*);
translateCpdma(cpDmaCfgs[cpdma].rxFlowRegs, CSL_Cppidma_rx_flow_configRegs*);
}
if ((result = Cppi_init (&translatedCppiGblCfgParams)) != CPPI_SOK){
printf ("Error initializing CPPI LLD, Error code : %d\n", result);
abort();
}
/* Setup memory regions */
/* Setup DATA region */
result = setup_region(
data_desc_base,
DATA_DESC_SIZE, DATA_DESC_NUM,
0,
DATA_REG_NUM);
if (result) abort();
/* Setup CTRL region */
result = setup_region(
ctrl_desc_base,
CTRL_DESC_SIZE, CTRL_DESC_NUM,
DATA_DESC_NUM,
CTRL_REG_NUM);
if (result) abort();
/* Setup TRACE region */
result = setup_region(
trace_desc_base,
TRACE_DESC_SIZE, TRACE_DESC_NUM,
DATA_DESC_NUM+CTRL_DESC_NUM,
TRACE_REG_NUM);
if (result) abort();
/* Setup FFTC region */
result = setup_region(
fftc_desc_base,
FFTC_DESC_SIZE, FFTC_DESC_NUM,
DATA_DESC_NUM+CTRL_DESC_NUM+TRACE_DESC_NUM,
FFTC_REG_NUM);
if (result) abort();
/* Setup the driver for this FFTC peripheral instance number. */
/* Set up the FFTC CPDMA configuration */
memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
cpdmaCfg.dmaNum = Cppi_CpDma_FFTC_A_CPDMA;
/* Initialize FFTC CPDMA */
if ((hCppi[0] = Cppi_open (&cpdmaCfg)) == NULL){
printf ("Error initializing CPPI for FFTC CPDMA %d\n", cpdmaCfg.dmaNum);
abort();
}
/* Disable FFTC CDMA loopback */
if (Cppi_setCpdmaLoopback (hCppi[0], 0) != CPPI_SOK){
printf ("Error disabling loopback for FFTC CPDMA %d\n", cpdmaCfg.dmaNum);
abort();
}
memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
cpdmaCfg.dmaNum = Cppi_CpDma_FFTC_B_CPDMA;
if ((hCppi[1] = Cppi_open (&cpdmaCfg)) == NULL){
printf ("Error initializing CPPI for FFTC CPDMA %d\n", cpdmaCfg.dmaNum);
abort();
}
/* Disable FFTC CDMA loopback */
if (Cppi_setCpdmaLoopback (hCppi[1], 0) != CPPI_SOK){
printf ("Error disabling loopback for FFTC CPDMA %d\n", cpdmaCfg.dmaNum);
abort();
}
fftc_a_cfg_regs->CONFIG = 0;
fftc_b_cfg_regs->CONFIG = 0;
// CSL_FMK (FFTC_CONFIG_Q3_FLOWID_OVERWRITE, 0) |
// CSL_FMK (FFTC_CONFIG_Q2_FLOWID_OVERWRITE, 0) |
// CSL_FMK (FFTC_CONFIG_Q1_FLOWID_OVERWRITE, 0) |
// CSL_FMK (FFTC_CONFIG_Q0_FLOWID_OVERWRITE, 0) |
// CSL_FMK (FFTC_CONFIG_STARVATION_PERIOD, 0) |
// CSL_FMK (FFTC_CONFIG_QUEUE_3_PRIORITY, 0) |
// CSL_FMK (FFTC_CONFIG_QUEUE_2_PRIORITY, 0) |
// CSL_FMK (FFTC_CONFIG_QUEUE_1_PRIORITY, 0) |
// CSL_FMK (FFTC_CONFIG_QUEUE_0_PRIORITY, 0) |
// CSL_FMK (FFTC_CONFIG_FFT_DISABLE, 0);
/* Emptying Queues */
/* Tx FFTC */
Qmss_queueEmpty(QMSS_FFTC_A_QUEUE_BASE);
for(i=QUEUE_FIRST; i<=QUEUE_LAST; i++){
Qmss_queueEmpty(i);
}
/* Populate free queues */
for(i=0; i<DATA_DESC_NUM; i++){
Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)data_desc_base + i*DATA_DESC_SIZE);
Osal_DescBeginMemAccess(mono_pkt, DATA_DESC_SIZE);
Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA};
Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC);
Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER);
Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, DATA_DESC_SIZE);
Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue);
/* Sync Descriptor */
Osal_DescEndMemAccess(mono_pkt, DATA_DESC_SIZE);
Qmss_queuePushDescSize(QUEUE_FREE_DATA, mono_pkt, DATA_DESC_SIZE);
}
for(i=0; i<CTRL_DESC_NUM; i++){
Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)ctrl_desc_base + i*CTRL_DESC_SIZE);
Osal_DescBeginMemAccess(mono_pkt, CTRL_DESC_SIZE);
Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA};
Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC);
Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER);
Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, CTRL_DESC_SIZE);
Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue);
/* Sync Descriptor */
Osal_DescEndMemAccess(mono_pkt, CTRL_DESC_SIZE);
Qmss_queuePushDescSize(QUEUE_FREE_CTRL, mono_pkt, CTRL_DESC_SIZE);
}
for(i=0; i<TRACE_DESC_NUM; i++){
Cppi_Desc* mono_pkt = (Cppi_Desc *) ((int)trace_desc_base + i*TRACE_DESC_SIZE);
Osal_DescBeginMemAccess(mono_pkt, TRACE_DESC_SIZE);
Qmss_Queue freeQueue = {0, QUEUE_FREE_DATA};
Cppi_setDescType( mono_pkt, Cppi_DescType_MONOLITHIC);
Cppi_setDataOffset( Cppi_DescType_MONOLITHIC, mono_pkt, PACKET_HEADER);
Cppi_setPacketLen( Cppi_DescType_MONOLITHIC, mono_pkt, TRACE_DESC_SIZE);
Cppi_setReturnQueue(Cppi_DescType_MONOLITHIC, mono_pkt, freeQueue);
/* Sync Descriptor */
Osal_DescEndMemAccess(mono_pkt, TRACE_DESC_SIZE);
Qmss_queuePushDescSize(QUEUE_FREE_TRACE, mono_pkt, TRACE_DESC_SIZE);
}
for(i=0; i<FFTC_DESC_NUM; i++){
Cppi_Desc * host_pkt = (Cppi_Desc *) ((int)fftc_desc_base + i*FFTC_DESC_SIZE);
Osal_DescBeginMemAccess(host_pkt, FFTC_DESC_SIZE);
memset(host_pkt, 0, FFTC_DESC_SIZE);
Qmss_Queue queue = {0, QUEUE_FREE_FFTC};
Cppi_setDescType( host_pkt, Cppi_DescType_HOST);
Cppi_setReturnPolicy( Cppi_DescType_HOST, host_pkt, Cppi_ReturnPolicy_RETURN_BUFFER);
Cppi_setReturnPushPolicy( Cppi_DescType_HOST, host_pkt, Qmss_Location_TAIL);
Cppi_setPSLocation( Cppi_DescType_HOST, host_pkt, Cppi_PSLoc_PS_IN_DESC);
Cppi_setReturnQueue( Cppi_DescType_HOST, host_pkt, queue);
((Cppi_HostDesc*)host_pkt)->nextBDPtr = 0;
/* Sync Descriptor */
Osal_DescEndMemAccess(host_pkt, FFTC_DESC_SIZE);
Qmss_queuePushDescSize(QUEUE_FREE_FFTC,host_pkt,FFTC_DESC_SIZE);
}
configureRxFlow(0);
configureRxFlow(1);
configureTxChan(0);
configureTxChan(1);
configureRxChan(0);
configureRxChan(1);
/* Finally, enable the Tx channel so that we can start sending
* data blocks to FFTC engine.
*/
Cppi_channelEnable (hCppiTxChan[0]);
Cppi_channelEnable (hCppiTxChan[1]);
Cppi_channelEnable (hCppiRxChan[0]);
Cppi_channelEnable (hCppiRxChan[1]);
configureFFTRegs(fftc_a_cfg_regs);
configureFFTRegs(fftc_b_cfg_regs);
}
