// f0 - f7 use this table
// note, the manual shows both src/dst opcodes in the same table as there's no overlap, but they're not compatible
void tlcs870_device::do_dstprefixtype_opcode(const uint8_t opbyte0)
{
m_cycles = get_base_srcdst_cycles(opbyte0 & 0x7); // set base number of cycles based on dst prefix mode
uint16_t dstaddr;
// (x) and (HL+d) require an immediate value
if ((opbyte0 == 0xf0) || (opbyte0 == 0xf4))
{
dstaddr = get_addr((opbyte0 & 0x7), READ8());
}
else
{
dstaddr = get_addr((opbyte0 & 0x7), 0);
}
const uint8_t opbyte1 = READ8();
// these are illegal prefixes for dst, undefined behavior at least
if ((opbyte0 == 0xf1) || (opbyte0 == 0xf5))
{
do_f0_to_f7_oprand_illegal_opcode(opbyte0, opbyte1, dstaddr);
}
switch (opbyte1)
{
case 0x10: case 0x11: case 0x12: case 0x13:
do_LD_indst_rr(opbyte0, opbyte1, dstaddr); break;
case 0x2c:
do_LD_indst_n(opbyte0, opbyte1, dstaddr); break;
case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
do_LD_indst_r(opbyte0, opbyte1, dstaddr); break;
default:
do_f0_to_f7_oprand_illegal_opcode(opbyte0, opbyte1, dstaddr); break;
}
}
static void I486OP(cmpxchg_rm8_r8)(i386_state *cpustate) // Opcode 0x0f b0
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
STORE_RM8(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG8(AL) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT8 dst = READ8(cpustate,ea);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
WRITE8(cpustate,modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG8(AL) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
void i386_device::i486_cmpxchg_rm8_r8() // Opcode 0x0f b0
{
UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
STORE_RM8(modrm, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG8(AL) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
// TODO: Check write if needed
UINT32 ea = GetEA(modrm,0);
UINT8 dst = READ8(ea);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
WRITE8(ea, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG8(AL) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
SeqTrigSrc
evgSeqRam::getTrigSrc() const {
SeqTrigSrc trigSrc = (SeqTrigSrc)READ8(m_pReg, SeqTrigSrc(m_id));
if(trigSrc == SoftRam0 || trigSrc == SoftRam1){
trigSrc = Software;
}
if(trigSrc == ExtRam0 || trigSrc == ExtRam1) {
evgInput* inp = 0;
for(int i = 0; i < evgNumFrontInp && inp == 0; i++)
inp = findSeqExtTrig(m_owner->getInput(i, FrontInp));
for(int i = 0; i < evgNumUnivInp && inp == 0; i++)
inp = findSeqExtTrig(m_owner->getInput(i, UnivInp));
for(int i = 0; i < evgNumRearInp && inp == 0; i++)
inp = findSeqExtTrig(m_owner->getInput(i, RearInp));
if(inp != 0)
trigSrc = (SeqTrigSrc)
((inp->getNum()*4 + (epicsUInt32)inp->getType()) + 40);
}
return trigSrc;
}
void tlcs870_device::do_ALUOP_g_n(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
ADDC g, n 1110 1ggg 0111 0000 nnnn nnnn C Z C H 3
ADD g, n 1110 1ggg 0111 0001 nnnn nnnn C Z C H 3
SUBB g, n 1110 1ggg 0111 0010 nnnn nnnn C Z C H 3
SUB g, n 1110 1ggg 0111 0011 nnnn nnnn C Z C H 3
AND g, n 1110 1ggg 0111 0100 nnnn nnnn Z Z - - 3
XOR g, n 1110 1ggg 0111 0101 nnnn nnnn Z Z - - 3
OR g, n 1110 1ggg 0111 0110 nnnn nnnn Z Z - - 3
CMP g, n 1110 1ggg 0111 0111 nnnn nnnn Z Z C H 3
*/
m_cycles = 3;
const int aluop = (opbyte1 & 0x7);
const uint8_t n = READ8();
const uint8_t result = do_alu_8bit(aluop, get_reg8(opbyte0 & 0x7), n);
if (aluop != 0x07) // CMP doesn't write back
{
set_reg8(opbyte0 & 0x7, result);
}
}
std::vector<epicsUInt8>
evgSeqRam::getEventCode() {
std::vector<epicsUInt8> eventCode(2048, 0);
for(unsigned int i = 0; i < eventCode.size(); i++)
eventCode[i] = READ8(m_pReg, SeqRamEvent(m_id,i));
return eventCode;
}
PLLBandwidth
evgEvtClk::getPLLBandwidth() const {
epicsUInt8 bw;
bw = (READ8(m_pReg, ClockSource) & EVG_CLK_BW); // read and mask out the PLL BW value
bw = bw >> EVG_CLK_BW_shift; // shift appropriately
return (PLLBandwidth)bw;
}
void
evgEvtClk::setSource (epicsUInt16 source) {
epicsUInt8 clkReg, regMap = 0;
epicsUInt32 version;
version = READ32(m_pReg, FWVersion);
version &= FWVersion_ver_mask;
if ((RFClockReference) source >= RFClockReference_PXIe100 && version < EVG_FCT_MIN_FIRMWARE ) {
throw std::out_of_range("RF clock source you selected does not exist in this firmware version.");
}
else if ((RFClockReference) source >= RFClockReference_ExtDownrate && version < EVG_MIN_FIRMWARE_REDUCECLK ) {
throw std::out_of_range("RF clock source you selected does not exist in this firmware version.");
}
switch ((RFClockReference) source) {
case RFClockReference_Internal:
regMap = EVG_CLK_SRC_INTERNAL;
break;
case RFClockReference_External:
regMap = EVG_CLK_SRC_EXTERNAL;
break;
case RFClockReference_PXIe100:
regMap = EVG_CLK_SRC_PXIE100;
break;
case RFClockReference_PXIe10:
regMap = EVG_CLK_SRC_PXIE10;
break;
case RFClockReference_Recovered:
regMap = EVG_CLK_SRC_RECOVERED;
break;
case RFClockReference_ExtDownrate:
regMap = EVG_CLK_SRC_EXTDOWNRATE;
break;
case RFClockReference_RecoverHalved:
regMap = EVG_CLK_SRC_RECOVERHALVED;
break;
default:
throw std::out_of_range("RF clock source you selected does not exist.");
break;
}
clkReg = READ8(m_pReg, ClockSource); // read register content
clkReg &= ~EVG_CLK_SRC_SEL; // clear old clock source
clkReg |= regMap; // set new clock source
WRITE8(m_pReg, ClockSource, clkReg); // write the new value to the register
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Byte value read from emulator memory.
REMARKS:
Reads a byte value from the emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
u8 X86API BE_rdb(
u32 addr)
{
u8 val = 0;
if (addr < M.mem_size) {
READ8(M.mem_base + addr, val);
} else if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
READ8(_BE_env.biosmem_base + addr - 0xC0000, val);
} else if (addr >= 0xA0000 && addr < 0xC0000) {
READ8(_BE_env.busmem_base + addr - 0xA0000, val);
} else if (addr >= 0xf0000 && addr < SYS_SIZE) {
READ8(_BE_env.sysmem_base + addr - 0xf0000, val);
}else {
printf("mem_read: address %#x out of range!\n", addr);
HALT_SYS();
}
DB( if (DEBUG_MEM())
printf("%#08x 1 -> %#x\n", addr, val);)
return val;
static
long write_gain(mbboRecord* prec)
{
xy566 *card=prec->dpvt;
short chan=prec->out.value.vmeio.signal;
if(chan < 0 || chan > card->nchan)
return 1;
WRITE8(card->base, XY566_GAIN(chan), prec->rval);
prec->rbv=READ8(card->base, XY566_GAIN(chan));
return 0;
}
void
evgEvtClk::setPLLBandwidth(PLLBandwidth pllBandwidth) {
epicsUInt8 clkCtrl;
epicsUInt8 bw;
if(pllBandwidth > PLLBandwidth_MAX){
throw std::out_of_range("PLL bandwith you selected is not available.");
}
bw = (epicsUInt8)pllBandwidth;
bw = bw << EVG_CLK_BW_shift; // shift appropriately
clkCtrl = READ8(m_pReg, ClockSource); // read register content
clkCtrl &= ~EVG_CLK_BW; // clear bw_sel
clkCtrl |= bw; // OR bw sel value
WRITE8(m_pReg, ClockSource, clkCtrl); // write the new value to the register
}
/* readonly attribute PRTime lastModifiedTime; */
NS_IMETHODIMP nsZipHeader::GetLastModifiedTime(PRTime *aLastModifiedTime)
{
NS_ASSERTION(mInited, "Not initalised");
// Try to read timestamp from extra field
PRUint16 blocksize;
const PRUint8 *tsField = GetExtraField(ZIP_EXTENDED_TIMESTAMP_FIELD, PR_FALSE, &blocksize);
if (tsField && blocksize >= 5) {
PRUint32 pos = 4;
PRUint8 flags;
flags = READ8(tsField, &pos);
if (flags & ZIP_EXTENDED_TIMESTAMP_MODTIME) {
*aLastModifiedTime = (PRTime)(READ32(tsField, &pos))
* PR_USEC_PER_SEC;
return NS_OK;
}
}
// Use DOS date/time fields
// Note that on DST shift we can't handle correctly the hour that is valid
// in both DST zones
PRExplodedTime time;
time.tm_usec = 0;
time.tm_hour = (mTime >> 11) & 0x1F;
time.tm_min = (mTime >> 5) & 0x3F;
time.tm_sec = (mTime & 0x1F) * 2;
time.tm_year = (mDate >> 9) + 1980;
time.tm_month = ((mDate >> 5) & 0x0F) - 1;
time.tm_mday = mDate & 0x1F;
time.tm_params.tp_gmt_offset = 0;
time.tm_params.tp_dst_offset = 0;
PR_NormalizeTime(&time, PR_GMTParameters);
time.tm_params.tp_gmt_offset = PR_LocalTimeParameters(&time).tp_gmt_offset;
PR_NormalizeTime(&time, PR_GMTParameters);
time.tm_params.tp_dst_offset = PR_LocalTimeParameters(&time).tp_dst_offset;
*aLastModifiedTime = PR_ImplodeTime(&time);
return NS_OK;
}
static void I486OP(xadd_rm8_r8)(i386_state *cpustate) // Opcode 0x0f c0
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
STORE_RM16(modrm, dst + src);
STORE_REG16(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_REG);
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT8 dst = READ8(cpustate,ea);
UINT8 src = LOAD_REG8(modrm);
WRITE8(cpustate,ea, dst + src);
STORE_REG8(modrm, dst);
CYCLES(cpustate,CYCLES_XADD_REG_MEM);
}
}
void i386_device::i486_xadd_rm8_r8() // Opcode 0x0f c0
{
UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
STORE_REG8(modrm, dst);
STORE_RM8(modrm, dst + src);
CYCLES(CYCLES_XADD_REG_REG);
} else {
UINT32 ea = GetEA(modrm,1);
UINT8 dst = READ8(ea);
UINT8 src = LOAD_REG8(modrm);
WRITE8(ea, dst + src);
STORE_REG8(modrm, dst);
CYCLES(CYCLES_XADD_REG_MEM);
}
}
epicsUInt16
evgEvtClk::getSource() const {
epicsUInt8 clkReg, source;
clkReg = READ8(m_pReg, ClockSource);
clkReg &= EVG_CLK_SRC_SEL;
switch (clkReg) {
case EVG_CLK_SRC_INTERNAL:
source = (epicsUInt8)RFClockReference_Internal;
break;
case EVG_CLK_SRC_EXTERNAL:
source = (epicsUInt8)RFClockReference_External;
break;
case EVG_CLK_SRC_PXIE100:
source = (epicsUInt8)RFClockReference_PXIe100;
break;
case EVG_CLK_SRC_PXIE10:
source = (epicsUInt8)RFClockReference_PXIe10;
break;
case EVG_CLK_SRC_RECOVERED:
source = (epicsUInt8)RFClockReference_Recovered;
break;
case EVG_CLK_SRC_EXTDOWNRATE:
source = (epicsUInt8)RFClockReference_ExtDownrate;
break;
case EVG_CLK_SRC_RECOVERHALVED:
source = (epicsUInt8)RFClockReference_RecoverHalved;
break;
default:
throw std::out_of_range("Cannot read valid RF clock source.");
break;
}
return source;
}
void tlcs870_device::do_LD_indst_n(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t dstaddr)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
LD (x), n not listed, redundant encoding? ? ? ? ? ?
LD (PC+A), n invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
LD (DE), n 1111 0010 0010 1100 nnnn nnnn 1 - - - 4
LD (HL), n not listed, redundant encoding? ? ? ? ? ?
LD (HL+d), n 1111 0100 dddd dddd 0010 1100 nnnn nnnn 1 - - - 6
LD (HL+C), n invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
LD (HL+), n 1111 0110 0010 1100 nnnn nnnn 1 - - - 5
LD (-HL), n 1111 0111 0010 1100 nnnn nnnn 1 - - - 5
aka (dst),n
(dst) can only be (DE), (HL+), (-HL), or (HL+d) because (x) and (HL) are redundant encodings?
*/
m_cycles += 4;
const uint16_t n = READ8();
WM8(dstaddr, n);
set_JF();
}
static
long write_output(boRecord* prec)
{
xy220 *priv=prec->dpvt;
short line=prec->out.value.vmeio.signal;
int port=line/8;
int bit=line%8;
epicsUInt8 mask=1<<bit;
epicsUInt8 val;
if(line<0 || port>XY220_NPORTS){
errMessage(errlogMajor,"I/O bit number out of range");
return 1;
}
epicsMutexMustLock(priv->guard);
val=READ8(priv->base, XY220_PORT(port));
if(dbg220>0)
printf("%lx read %02x ",(unsigned long)prec,val);
if(prec->rval)
val|=mask;
else
val&=~mask;
if(dbg220>0)
printf("write %02x\n",val);
WRITE8(priv->base, XY220_PORT(port), val);
epicsMutexUnlock(priv->guard);
return 0;
}
static void HandleMemSingle( data32_t insn )
{
data32_t rn, rnv, off, rd;
/* Fetch the offset */
if (insn & INSN_I)
{
off = decodeShift(insn, NULL);
}
else
{
off = insn & INSN_SDT_IMM;
}
/* Calculate Rn, accounting for PC */
rn = (insn & INSN_RN) >> INSN_RN_SHIFT;
// if (rn==0xf) logerror("%08x: Source R15\n",R15);
if (insn & INSN_SDT_P)
{
/* Pre-indexed addressing */
if (insn & INSN_SDT_U)
{
rnv = (GetRegister(rn) + off);
}
else
{
rnv = (GetRegister(rn) - off);
}
if (insn & INSN_SDT_W)
{
SetRegister(rn,rnv);
//check writeback???
}
else if (rn == eR15)
{
rnv = (rnv & ADDRESS_MASK) + 8;
}
}
else
{
/* Post-indexed addressing */
if (rn == eR15)
{
rnv = (R15 & ADDRESS_MASK) + 8;
}
else
{
rnv = GetRegister(rn);
}
}
/* Do the transfer */
rd = (insn & INSN_RD) >> INSN_RD_SHIFT;
if (insn & INSN_SDT_L)
{
/* Load */
if (insn & INSN_SDT_B)
{
SetRegister(rd,(data32_t) READ8(rnv));
}
else
{
if (rd == eR15)
{
if (ARM_DEBUG_CORE)
logerror("%08x: LDR to R15\n",R15);
R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
R15 -= 4;
}
else
{
SetRegister(rd,READ32(rnv));
}
}
}
else
{
/* Store */
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in byte mode\n");
WRITE8(rnv, (data8_t) GetRegister(rd) & 0xffu);
}
else
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in 32bit mode\n");
WRITE32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
}
}
/* Do post-indexing writeback */
if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/)
{
if (insn & INSN_SDT_U)
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
//todo: check for offs... ?
}
else {
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
SetRegister(rn,(rnv + off));
}
}
else
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
// logerror("Arm %08x: LDR style with rn==rn\n",R15);
}
else {
SetRegister(rn,(rnv - off));
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
}
}
}
// arm_check_irq_state()
} /* HandleMemSingle */
MCFG_DEVICE_ADD( "dma8237_2", AM9517A, XTAL_14_31818MHz/3 )
MCFG_I8237_OUT_HREQ_CB(WRITELINE(southbridge_device, pc_dma_hrq_changed))
MCFG_I8237_IN_MEMR_CB(READ8(southbridge_device, pc_dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(southbridge_device, pc_dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(southbridge_device, pc_dma8237_5_dack_r))
MCFG_I8237_IN_IOR_2_CB(READ8(southbridge_device, pc_dma8237_6_dack_r))
MCFG_I8237_IN_IOR_3_CB(READ8(southbridge_device, pc_dma8237_7_dack_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(southbridge_device, pc_dma8237_5_dack_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(southbridge_device, pc_dma8237_6_dack_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(southbridge_device, pc_dma8237_7_dack_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(southbridge_device, pc_dack4_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(southbridge_device, pc_dack5_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(southbridge_device, pc_dack6_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(southbridge_device, pc_dack7_w))
MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE(":maincpu", 0), VCC, READ8(southbridge_device, get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir2_w), GND, NULL )
MCFG_DEVICE_ADD("keybc", AT_KEYBOARD_CONTROLLER, XTAL_12MHz)
MCFG_AT_KEYBOARD_CONTROLLER_SYSTEM_RESET_CB(INPUTLINE(":maincpu", INPUT_LINE_RESET))
MCFG_AT_KEYBOARD_CONTROLLER_GATE_A20_CB(INPUTLINE(":maincpu", INPUT_LINE_A20))
MCFG_AT_KEYBOARD_CONTROLLER_INPUT_BUFFER_FULL_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_CLOCK_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, clock_write_from_mb))
MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_DATA_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, data_write_from_mb))
MCFG_DEVICE_ADD("pc_kbdc", PC_KBDC, 0)
MCFG_PC_KBDC_OUT_CLOCK_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_clock_w))
MCFG_PC_KBDC_OUT_DATA_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_data_w))
MCFG_PC_KBDC_SLOT_ADD("pc_kbdc", "kbd", pc_at_keyboards, STR_KBD_MICROSOFT_NATURAL)
MCFG_DS12885_ADD("rtc")
MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir0_w))
{
map(0x0000, 0x07ff).rom().region(I8035_Z5_TAG, 0);
}
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
MACHINE_CONFIG_START(abc99_device::device_add_mconfig)
// keyboard CPU
MCFG_DEVICE_ADD(I8035_Z2_TAG, I8035, XTAL(6'000'000)/3) // from Z5 T0 output
MCFG_DEVICE_PROGRAM_MAP(abc99_z2_mem)
MCFG_DEVICE_IO_MAP(abc99_z2_io)
MCFG_MCS48_PORT_P1_OUT_CB(WRITE8(*this, abc99_device, z2_p1_w))
MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, abc99_device, z2_p2_r))
MCFG_MCS48_PORT_T0_IN_CB(READLINE(*this, abc99_device, z2_t0_r))
MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, abc99_device, z2_t1_r))
// mouse CPU
MCFG_DEVICE_ADD(I8035_Z5_TAG, I8035, XTAL(6'000'000))
MCFG_DEVICE_PROGRAM_MAP(abc99_z5_mem)
//MCFG_MCS48_PORT_P1_IN_CB(READ8(*this, abc99_device, z5_p1_r))
//MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, abc99_device, z5_p2_w))
//MCFG_MCS48_PORT_T0_CLK_CUSTOM() // Z2 CLK
//MCFG_MCS48_PORT_T1_IN_CB(READ8(*this, abc99_device, z5_t1_r))
MCFG_DEVICE_DISABLE() // HACK fix for broken serial I/O
// sound hardware
SPEAKER(config, "mono").front_center();
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND, 0)
UINT16 mc68hc11_cpu_device::READ16(UINT32 address)
{
return (READ8(address) << 8) | (READ8(address+1));
}
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(wd7600_device, dma1_dack3_w))
MCFG_DEVICE_ADD("dma2", AM9517A, 0)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(wd7600_device, dma2_hreq_w))
MCFG_I8237_IN_MEMR_CB(READ8(wd7600_device, dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(wd7600_device, dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(wd7600_device, dma2_ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(wd7600_device, dma2_ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(wd7600_device, dma2_ior3_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(wd7600_device, dma2_iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(wd7600_device, dma2_iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(wd7600_device, dma2_iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(wd7600_device, dma2_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(wd7600_device, dma2_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(wd7600_device, dma2_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(wd7600_device, dma2_dack3_w))
MCFG_PIC8259_ADD("intc1", WRITELINE(wd7600_device, pic1_int_w), VCC, READ8(wd7600_device, pic1_slave_ack_r))
MCFG_PIC8259_ADD("intc2", DEVWRITELINE("intc1", pic8259_device, ir2_w), GND, NULL)
MCFG_DEVICE_ADD("ctc", PIT8254, 0)
MCFG_PIT8253_CLK0(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("intc1", pic8259_device, ir0_w))
MCFG_PIT8253_CLK1(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT1_HANDLER(WRITELINE(wd7600_device, ctc_out1_w))
MCFG_PIT8253_CLK2(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(wd7600_device, ctc_out2_w))
MCFG_DS12885_ADD("rtc")
MCFG_MC146818_IRQ_HANDLER(WRITELINE(wd7600_device, rtc_irq_w))
MCFG_MC146818_CENTURY_INDEX(0x32)
MACHINE_CONFIG_END
MCFG_DEVICE_ADD("lcdc", HD61830, XTAL(4'915'200)/2/2) // unknown clock
MCFG_VIDEO_SET_SCREEN("screen")
/* sound hardware */
SPEAKER(config, "mono").front_center();
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
/* Devices */
MCFG_DEVICE_ADD("rtc", MM58274C, 0)
// this is all a guess
MCFG_MM58274C_MODE24(0) // 12 hour
MCFG_MM58274C_DAY1(1) // monday
MCFG_NSC810_ADD("iotimer",XTAL(4'000'000),XTAL(4'000'000))
MCFG_NSC810_PORTA_READ(READ8(*this, hunter2_state,keyboard_r))
MCFG_NSC810_PORTB_READ(READ8(*this, hunter2_state,serial_dsr_r))
MCFG_NSC810_PORTB_WRITE(WRITE8(*this, hunter2_state,keyboard_w))
MCFG_NSC810_PORTC_READ(READ8(*this, hunter2_state,serial_rx_r))
MCFG_NSC810_TIMER0_OUT(WRITELINE(*this, hunter2_state,timer0_out))
MCFG_NSC810_TIMER1_OUT(WRITELINE(*this, hunter2_state,timer1_out))
RS232_PORT(config, m_rs232, default_rs232_devices, nullptr);
m_rs232->cts_handler().set(FUNC(hunter2_state::cts_w));
m_rs232->rxd_handler().set(FUNC(hunter2_state::rxd_w));
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
ADDRESS_MAP_BANK(config, "bank1").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
ADDRESS_MAP_BANK(config, "bank2").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
ADDRESS_MAP_BANK(config, "bank3").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
m_bus->ifc_w(BIT(data, 0)); m_bus->srq_w(BIT(data, 1)); m_exrom = !BIT(data, 3); m_roml_sel = BIT(data, 4); } //------------------------------------------------- // device_add_mconfig - add device configuration //------------------------------------------------- MACHINE_CONFIG_START(c64_ieee488_device::device_add_mconfig) MCFG_DEVICE_ADD(MOS6525_TAG, TPI6525, 0) MCFG_TPI6525_IN_PA_CB(READ8(*this, c64_ieee488_device, tpi_pa_r)) MCFG_TPI6525_OUT_PA_CB(WRITE8(*this, c64_ieee488_device, tpi_pa_w)) MCFG_TPI6525_IN_PB_CB(READ8(IEEE488_TAG, ieee488_device, dio_r)) MCFG_TPI6525_OUT_PB_CB(WRITE8(IEEE488_TAG, ieee488_device, dio_w)) MCFG_TPI6525_IN_PC_CB(READ8(*this, c64_ieee488_device, tpi_pc_r)) MCFG_TPI6525_OUT_PC_CB(WRITE8(*this, c64_ieee488_device, tpi_pc_w)) MCFG_CBM_IEEE488_ADD(nullptr) MCFG_C64_PASSTHRU_EXPANSION_SLOT_ADD() MACHINE_CONFIG_END //************************************************************************** // LIVE DEVICE //**************************************************************************
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(cs4031_device, dma1_dack3_w))
MCFG_DEVICE_ADD("dma2", AM9517A, 0)
MCFG_I8237_OUT_HREQ_CB(WRITELINE(cs4031_device, dma2_hreq_w))
MCFG_I8237_IN_MEMR_CB(READ8(cs4031_device, dma_read_word))
MCFG_I8237_OUT_MEMW_CB(WRITE8(cs4031_device, dma_write_word))
MCFG_I8237_IN_IOR_1_CB(READ8(cs4031_device, dma2_ior1_r))
MCFG_I8237_IN_IOR_2_CB(READ8(cs4031_device, dma2_ior2_r))
MCFG_I8237_IN_IOR_3_CB(READ8(cs4031_device, dma2_ior3_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(cs4031_device, dma2_iow1_w))
MCFG_I8237_OUT_IOW_2_CB(WRITE8(cs4031_device, dma2_iow2_w))
MCFG_I8237_OUT_IOW_3_CB(WRITE8(cs4031_device, dma2_iow3_w))
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(cs4031_device, dma2_dack0_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(cs4031_device, dma2_dack1_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(cs4031_device, dma2_dack2_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(cs4031_device, dma2_dack3_w))
MCFG_PIC8259_ADD("intc1", WRITELINE(cs4031_device, intc1_int_w), VCC, READ8(cs4031_device, intc1_slave_ack_r))
MCFG_PIC8259_ADD("intc2", DEVWRITELINE("intc1", pic8259_device, ir2_w), GND, NOOP)
MCFG_DEVICE_ADD("ctc", PIT8254, 0)
MCFG_PIT8253_CLK0(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("intc1", pic8259_device, ir0_w))
MCFG_PIT8253_CLK1(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT1_HANDLER(WRITELINE(cs4031_device, ctc_out1_w))
MCFG_PIT8253_CLK2(XTAL_14_31818MHz / 12)
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(cs4031_device, ctc_out2_w))
MCFG_DS12885_ADD("rtc")
MCFG_MC146818_IRQ_HANDLER(WRITELINE(cs4031_device, rtc_irq_w))
MCFG_MC146818_CENTURY_INDEX(0x32)
MACHINE_CONFIG_END
break;
}
}
void de_3b_state::machine_reset()
{
}
void de_3b_state::init_de_3b()
{
}
MACHINE_CONFIG_START(de_3b_state::de_3b)
/* basic machine hardware */
MCFG_DECOCPU_TYPE3B_ADD("decocpu",XTAL(8'000'000) / 2, ":maincpu")
MCFG_DECOCPU_DISPLAY(READ8(*this, de_3b_state,display_r),WRITE8(*this, de_3b_state,display_w))
MCFG_DECOCPU_SOUNDLATCH(WRITE8(*this, de_3b_state,sound_w))
MCFG_DECOCPU_SWITCH(READ8(*this, de_3b_state,switch_r),WRITE8(*this, de_3b_state,switch_w))
MCFG_DECOCPU_LAMP(WRITE8(*this, de_3b_state,lamps_w))
MCFG_DECOCPU_DMDSTATUS(READ8(*this, de_3b_state,dmd_status_r))
genpin_audio(config);
/* sound hardware */
MCFG_DECOBSMT_ADD(DECOBSMT_TAG)
MCFG_DECODMD_TYPE3_ADD("decodmd",":cpu3")
MACHINE_CONFIG_END
MACHINE_CONFIG_START(de_3b_state::detest)
WRITE8_MEMBER(ron_state::ay_pa_w)
{
}
MACHINE_CONFIG_START(ron_state::ron)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", Z80, MAIN_CLOCK)
MCFG_DEVICE_PROGRAM_MAP(ron_map)
MCFG_DEVICE_IO_MAP(ron_io)
MCFG_DEVICE_ADD("audiocpu", I8035, SOUND_CLOCK)
MCFG_DEVICE_PROGRAM_MAP(ron_audio_map)
MCFG_DEVICE_IO_MAP(ron_audio_io)
MCFG_MCS48_PORT_T0_CLK_DEVICE("aysnd")
MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, ron_state, audio_cmd_r))
MCFG_MCS48_PORT_P1_OUT_CB(WRITE8(*this, ron_state, audio_p1_w))
MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, ron_state, audio_p2_w))
MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, ron_state, audio_T1_r))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(ron_state, screen_update)
MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK, 320, 0, 256, 264, 0, 240)
MCFG_SCREEN_PALETTE("palette")
MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, ron_state, vblank_irq))
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_ron)
MCFG_PALETTE_ADD("palette", 8)
//MCFG_PALETTE_ADD("palette", 512)
, m_matrix(*this, "ROW.%X", 0)
, m_modifiers(*this, "MOD")
, m_rxd_cb(*this)
, m_txd(1U)
, m_bus(0U)
{
}
tiny_rom_entry const *kaypro_10_keyboard_device::device_rom_region() const
{
return ROM_NAME(kaypro_10_keyboard);
}
MACHINE_CONFIG_START(kaypro_10_keyboard_device::device_add_mconfig)
MCFG_DEVICE_ADD("mcu", I8049, 6_MHz_XTAL)
MCFG_MCS48_PORT_P1_IN_CB(READ8(*this, kaypro_10_keyboard_device, p1_r))
MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, kaypro_10_keyboard_device, p2_r))
MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, kaypro_10_keyboard_device, p2_w))
MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, kaypro_10_keyboard_device, t1_r))
MCFG_MCS48_PORT_BUS_IN_CB(READ8(*this, kaypro_10_keyboard_device, bus_r))
MCFG_MCS48_PORT_BUS_OUT_CB(WRITE8(*this, kaypro_10_keyboard_device, bus_w))
SPEAKER(config, "keyboard").front_center();
MCFG_DEVICE_ADD("bell", SPEAKER_SOUND)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "keyboard", 0.25)
MACHINE_CONFIG_END
ioport_constructor kaypro_10_keyboard_device::device_input_ports() const
{
(void)&INPUT_PORTS_NAME(kaypro_keyboard_bitshift);
return INPUT_PORTS_NAME(kaypro_keyboard_typewriter);
MCFG_HUC6260_NEXT_PIXEL_DATA_CB(READ16("huc6202", huc6202_device, next_pixel))
MCFG_HUC6260_TIME_TIL_NEXT_EVENT_CB(READ16("huc6202", huc6202_device, time_until_next_event))
MCFG_HUC6260_VSYNC_CHANGED_CB(WRITELINE("huc6202", huc6202_device, vsync_changed))
MCFG_HUC6260_HSYNC_CHANGED_CB(WRITELINE("huc6202", huc6202_device, hsync_changed))
MCFG_DEVICE_ADD( "huc6270_0", HUC6270, 0 )
MCFG_HUC6270_VRAM_SIZE(0x10000)
MCFG_HUC6270_IRQ_CHANGED_CB(INPUTLINE("maincpu", 0))
MCFG_DEVICE_ADD( "huc6270_1", HUC6270, 0 )
MCFG_HUC6270_VRAM_SIZE(0x10000)
MCFG_HUC6270_IRQ_CHANGED_CB(INPUTLINE("maincpu", 0))
MCFG_DEVICE_ADD( "huc6202", HUC6202, 0 )
MCFG_HUC6202_NEXT_PIXEL_0_CB(READ16("huc6270_0", huc6270_device, next_pixel))
MCFG_HUC6202_TIME_TIL_NEXT_EVENT_0_CB(READ16("huc6270_0", huc6270_device, time_until_next_event))
MCFG_HUC6202_VSYNC_CHANGED_0_CB(WRITELINE("huc6270_0", huc6270_device, vsync_changed))
MCFG_HUC6202_HSYNC_CHANGED_0_CB(WRITELINE("huc6270_0", huc6270_device, hsync_changed))
MCFG_HUC6202_READ_0_CB(READ8("huc6270_0", huc6270_device, read))
MCFG_HUC6202_WRITE_0_CB(WRITE8("huc6270_0", huc6270_device, write))
MCFG_HUC6202_NEXT_PIXEL_1_CB(READ16("huc6270_1", huc6270_device, next_pixel))
MCFG_HUC6202_TIME_TIL_NEXT_EVENT_1_CB(READ16("huc6270_1", huc6270_device, time_until_next_event))
MCFG_HUC6202_VSYNC_CHANGED_1_CB(WRITELINE("huc6270_1", huc6270_device, vsync_changed))
MCFG_HUC6202_HSYNC_CHANGED_1_CB(WRITELINE("huc6270_1", huc6270_device, hsync_changed))
MCFG_HUC6202_READ_1_CB(READ8("huc6270_1", huc6270_device, read))
MCFG_HUC6202_WRITE_1_CB(WRITE8("huc6270_1", huc6270_device, write))
MCFG_DEVICE_ADD("rtc", MSM6242, XTAL(32'768))
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
MCFG_DEVICE_ADD("oki", OKIM6295, PCE_MAIN_CLOCK/12, okim6295_device::PIN7_HIGH) /* unknown clock / pin 7 */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.00)
MCFG_I8237_IN_MEMR_CB(READ8(octopus_state,dma_read))
MCFG_I8237_OUT_MEMW_CB(WRITE8(octopus_state,dma_write))
//MCFG_I8237_IN_IOR_0_CB(NOOP)
MCFG_I8237_IN_IOR_1_CB(DEVREAD8("fdc",fd1793_t,data_r)) // FDC
//MCFG_I8237_IN_IOR_2_CB(NOOP)
//MCFG_I8237_IN_IOR_3_CB(NOOP)
//MCFG_I8237_OUT_IOW_0_CB(NOOP)
MCFG_I8237_OUT_IOW_1_CB(DEVWRITE8("fdc",fd1793_t,data_w)) // FDC
//MCFG_I8237_OUT_IOW_2_CB(NOOP)
//MCFG_I8237_OUT_IOW_3_CB(NOOP)
MCFG_I8237_OUT_DACK_0_CB(WRITELINE(octopus_state, dack4_w))
MCFG_I8237_OUT_DACK_1_CB(WRITELINE(octopus_state, dack5_w))
MCFG_I8237_OUT_DACK_2_CB(WRITELINE(octopus_state, dack6_w))
MCFG_I8237_OUT_DACK_3_CB(WRITELINE(octopus_state, dack7_w))
MCFG_PIC8259_ADD("pic_master", INPUTLINE("maincpu",0), VCC, READ8(octopus_state,get_slave_ack))
MCFG_PIC8259_ADD("pic_slave", DEVWRITELINE("pic_master",pic8259_device, ir7_w), GND, NOOP)
// RTC (MC146818 via i8255 PPI)
MCFG_DEVICE_ADD("ppi", I8255, 0)
MCFG_I8255_IN_PORTA_CB(READ8(octopus_state,rtc_r))
MCFG_I8255_IN_PORTB_CB(READ8(octopus_state,cntl_r))
MCFG_I8255_IN_PORTC_CB(READ8(octopus_state,gpo_r))
MCFG_I8255_OUT_PORTA_CB(WRITE8(octopus_state,rtc_w))
MCFG_I8255_OUT_PORTB_CB(WRITE8(octopus_state,cntl_w))
MCFG_I8255_OUT_PORTC_CB(WRITE8(octopus_state,gpo_w))
MCFG_MC146818_ADD("rtc", XTAL_32_768kHz)
MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic_slave",pic8259_device, ir2_w)) MCFG_DEVCB_INVERT
// Keyboard UART
MCFG_DEVICE_ADD("keyboard", I8251, 0)
