/*
* inbyte -- get a byte from the DUART RX buffer. This only reads
* from channel A
*/
char
inbyte (void)
{
while ((READREG (DUART_SRA) & 0x01) == 0x00)
;
return (READREG (DUART_RBA)); /* read the byte */
}
static void dumpRegs()
{
printf( "IBMR == 0x%08lx\n", READREG(IBMR));
printf( "IDBR == 0x%08lx\n", READREG(IDBR));
printf( "ICR == 0x%08lx\n", READREG(ICR));
printf( "ISR == 0x%08lx\n", READREG(ISR));
printf( "ISAR == 0x%08lx\n", READREG(ISAR));
}
ULONG MACH_DisplayVideo(ULONG BufferOffset) {
if (!(pRegs->chipflags&MACH_NEED_RESETUP)) {
WaitForIdle(2);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,SCALER_BUF0_OFFSET,BufferOffset);
pRegs->offset=BufferOffset;
return RC_SUCCESS;
}
WaitForIdle(12);
WRITEREG(MMIO,OVERLAY_SCALE_CNTL,pRegs->scale_cntl);
WRITEREG(MMIO,OVERLAY_SCALE_INC,pRegs->scale_inc);
WRITEREG(MMIO,VIDEO_FORMAT,pRegs->format);
WRITEREG(MMIO,SCALER_BUF0_PITCH,pRegs->pitch);
WRITEREG(MMIO,SCALER_HEIGHT_WIDTH,pRegs->height_width);
WRITEREG(MMIO,CAPTURE_CONFIG,pRegs->config);
WRITEREG(MMIO,OVERLAY_Y_X,pRegs->y_x);
WRITEREG(MMIO,OVERLAY_Y_X_END,pRegs->y_x_end);
WRITEREG(MMIO,SCALER_BUF0_OFFSET,BufferOffset);
pRegs->offset=BufferOffset;
WRITEREG(MMIO,OVERLAY_GRAPHICS_KEY_MSK,pRegs->key_msk);
WRITEREG(MMIO,OVERLAY_GRAPHICS_KEY_CLR,pRegs->key_clr);
WRITEREG(MMIO,OVERLAY_KEY_CNTL,pRegs->key_cntl);
pRegs->chipflags&=~MACH_NEED_RESETUP;
return RC_SUCCESS;
}
int snd_aw2_saa7146_is_using_digital_input(struct snd_aw2_saa7146 *chip)
{
unsigned int reg_val = READREG(GPIO_CTRL);
if ((reg_val & 0xFF) == 0x40)
return 1;
else
return 0;
}
irqreturn_t snd_aw2_saa7146_interrupt(int irq, void *dev_id)
{
unsigned int isr;
unsigned int iicsta;
struct snd_aw2_saa7146 *chip = dev_id;
isr = READREG(ISR);
if (!isr)
return IRQ_NONE;
WRITEREG(isr, ISR);
if (isr & (IIC_S | IIC_E)) {
iicsta = READREG(IICSTA);
WRITEREG(0x100, IICSTA);
}
if (isr & A1_out) {
if (arr_substream_it_playback_cb[1].p_it_callback != NULL) {
arr_substream_it_playback_cb[1].
p_it_callback(arr_substream_it_playback_cb[1].
p_callback_param);
}
}
if (isr & A2_out) {
if (arr_substream_it_playback_cb[0].p_it_callback != NULL) {
arr_substream_it_playback_cb[0].
p_it_callback(arr_substream_it_playback_cb[0].
p_callback_param);
}
}
if (isr & A1_in) {
if (arr_substream_it_capture_cb[0].p_it_callback != NULL) {
arr_substream_it_capture_cb[0].
p_it_callback(arr_substream_it_capture_cb[0].
p_callback_param);
}
}
return IRQ_HANDLED;
}
unsigned int snd_aw2_saa7146_get_hw_ptr_playback(struct snd_aw2_saa7146 *chip,
int stream_number,
unsigned char *start_addr,
unsigned int buffer_size)
{
long pci_adp = 0;
size_t ptr = 0;
if (stream_number == 0) {
pci_adp = READREG(PCI_ADP3);
ptr = pci_adp - (long)start_addr;
if (ptr == buffer_size)
ptr = 0;
}
if (stream_number == 1) {
pci_adp = READREG(PCI_ADP1);
ptr = pci_adp - (size_t) start_addr;
if (ptr == buffer_size)
ptr = 0;
}
return ptr;
}
unsigned int snd_aw2_saa7146_get_hw_ptr_capture(struct snd_aw2_saa7146 *chip,
int stream_number,
unsigned char *start_addr,
unsigned int buffer_size)
{
size_t pci_adp = 0;
size_t ptr = 0;
if (stream_number == 0) {
pci_adp = READREG(PCI_ADP2);
ptr = pci_adp - (size_t) start_addr;
if (ptr == buffer_size)
ptr = 0;
}
return ptr;
}
void snd_aw2_saa7146_pcm_trigger_stop_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
acon1 = READREG(ACON1);
if (stream_number == 0) {
/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
acon1 &= ~(3 * WS2_CTRL);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A2_OUT << 16), MC1);
} else if (stream_number == 1) {
/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
acon1 &= ~(3 * WS1_CTRL);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A1_OUT << 16), MC1);
}
}
void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
acon1 = READREG(ACON1);
if (stream_number == 0) {
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
acon1 |= 2 * WS2_CTRL;
WRITEREG(acon1, ACON1);
} else if (stream_number == 1) {
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
acon1 |= 1 * WS1_CTRL;
WRITEREG(acon1, ACON1);
}
}
void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
/* In aw8 driver, dma transfert is always active. It is
started and stopped in a larger "space" */
acon1 = READREG(ACON1);
if (stream_number == 0) {
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
acon1 |= 2 * WS2_CTRL;
WRITEREG(acon1, ACON1);
} else if (stream_number == 1) {
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
acon1 |= 1 * WS1_CTRL;
WRITEREG(acon1, ACON1);
}
}
ULONG MACH_CheckHW(void) {
static USHORT MACHList[]={0x4754,0x4755,0x475a,0x4757,
0x4756,0x4742,0x4744,0x4749,
0x4750,0x4751,0x4c49,0x4c42,
0x4c50,0x4c47,0x474d,0x4c4d};
ULONG i,rc,temp;
rc=pci_read_dword(&PciDevice,0,&temp);
if (rc) return RC_ERROR;
temp>>=16; //temp=PCI DEVICE ID
i=0;
while ((temp!=MACHList[i])&&(i<16)) i++;
if (i==16) return RC_ERROR;
rc=pci_read_dword(&PciDevice,0x10,&temp);
if (rc) return RC_ERROR;
temp&=0xfff00000;//mask out lower bits
MMIO=PhysToLin(temp+0x7ff800,0x800);
if (MMIO==NULL) return RC_ERROR;
//enable block 1 access
WaitForIdle(7);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,SCALER_COLOUR_CNTL, (0x00) | (0x10 << 8) | (0x10 << 16) );
WRITEREG(MMIO,SCALER_H_COEFF0, (0x00) | (0x20 << 8) );
WRITEREG(MMIO,SCALER_H_COEFF1, (0x0D) | (0x20 << 8) | (0x06 << 16) | (0x0D << 24) );
WRITEREG(MMIO,SCALER_H_COEFF2, (0x0D) | (0x1C << 8) | (0x0A << 16) | (0x0D << 24) );
WRITEREG(MMIO,SCALER_H_COEFF3, (0x0C) | (0x1A << 8) | (0x0E << 16) | (0x0C << 24) );
WRITEREG(MMIO,SCALER_H_COEFF4, (0x0C) | (0x14 << 8) | (0x14 << 16) | (0x0C << 24) );
pRegs->scale_cntl=0x0c; //filtering on, red temp=6500K
pRegs->chipflags|=MACH_NEED_RESETUP;
HideVideo=MACH_HideVideo;
VideoCaps=MACH_VideoCaps;
SetVideoAttr=MACH_SetVideoAttr;
GetVideoAttr=MACH_GetVideoAttr;
DisplayVideo=MACH_DisplayVideo;
SetupVideo=MACH_SetupVideo;
RestoreVideo=MACH_RestoreVideo;
return RC_SUCCESS;
}
static bool read( char *data, // out
unsigned &len ) // in+out
{
unsigned const max = len ;
len = 0 ;
WRITEREG(ICR,ICR_RESET); //
WRITEREG(ISR,0x7ff); // ack interrupts
usleep(1000);
WRITEREG(ICR,ICR_SLENABLE);
CLRREGBIT(ICR,ICR_UR_BIT);
bool worked = false ;
for( unsigned i = 0 ; !worked && ( i < 1 ); i++ ){
long long start = tickMs();
do {
unsigned long isr = READREG(ISR);
if( isr & ISR_SAD ){
if( isr & ISR_MASTER_RX ){
printf( "Master rx\n" );
break ;
}
if( isr & ISR_SSD ){
// SETREGBIT(ISR,ISR_SSD_BIT);
printf( "Slave stop: no data\n" );
return true ;
}
if( isr & ISR_ACKNAK ){
// SETREGBIT(ISR,ISR_SSD_BIT);
printf( "nak waiting for slave\n" );
SETREGBIT(ISR,ISR_ACKNAKBIT);
return true ;
}
SETREGBIT(ISR,9);
worked = true ;
break ;
}
else if( isr & ISR_BED ){
printf( "bus error\n" );
break ;
}
long long now = tickMs();
if( now-start > 2000 ){
printf( "timeout waiting for slave\n" );
dumpRegs();
break ;
}
} while( 1 );
if( !worked ){
printf( "retry\n" );
WRITEREG(ICR,ICR_RESET); //
usleep((i+1)*1000);
CLRREGBIT(ICR,ICR_UR_BIT);
usleep((i+1)*1000);
WRITEREG(ICR,ICR_SLENABLE);
}
}
do {
SETREGBIT(ICR,ICR_TB_BIT);
long long start = tickMs();
do { // wait for rx
unsigned long isr = READREG(ISR);
if( isr & ISR_IRF ){
char const byte = READREG(IDBR);
data[len++] = byte ;
SETREGBIT(ISR,ISR_IRF_BIT); // ack
if( isr & ISR_SSD ){
// SETREGBIT(ISR,ISR_SSD_BIT);
return true ;
}
break ;
} else if( isr & ISR_SSD ){
return true ;
}
long long now = tickMs();
if( now-start > 2000 ){
printf( "timeout waiting for data\n" );
return false ;
}
} while( 1 );
} while( 1 );
return true ;
}
//ISR(PCINT2_vect ){
void __vector_11(void){
/*Checking for the Pressed switch*/
//swPressed = ((~PORTK) & ((1<<PK0)|(1<<PK1)|(1<<PK2)|(1<<PK3)|(1<<PK4)|(1<<PK5)|(1<<PK6)|(1<<PK7)));
swPressed = READREG(PINK);
}
void _inline WaitForIdle(ULONG entries) {
while ((READREG(MMIO,FIFO_STAT)& 0xffff)>((ULONG)(0x8000 >> entries)))
{
}
}
ULONG MACH_HideVideo(void) {
WaitForIdle(4);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,OVERLAY_SCALE_CNTL,READREG(MMIO,OVERLAY_SCALE_CNTL)&0x3fffffff);
return RC_SUCCESS;
}
void board_putc(char c)
{
while ((READREG(ASC_FSTAT) & TXMASK) >> TXOFFSET);
WRITEREG(ASC_TBUF, c);
}
