void pin_set(uint pin, int value) {
if (pin == 16) {
int out_en = (pin_mode[pin] == GPIO_MODE_OUTPUT);
WRITE_PERI_REG(PAD_XPD_DCDC_CONF, (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | 1);
WRITE_PERI_REG(RTC_GPIO_CONF, READ_PERI_REG(RTC_GPIO_CONF) & ~1);
WRITE_PERI_REG(RTC_GPIO_ENABLE, (READ_PERI_REG(RTC_GPIO_ENABLE) & ~1) | out_en);
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & ~1) | value);
return;
}
uint32_t enable = 0;
uint32_t disable = 0;
switch (pin_mode[pin]) {
case GPIO_MODE_INPUT:
value = -1;
disable = 1;
break;
case GPIO_MODE_OUTPUT:
enable = 1;
break;
case GPIO_MODE_OPEN_DRAIN:
if (value == -1) {
return;
} else if (value == 0) {
enable = 1;
} else {
value = -1;
disable = 1;
}
break;
}
enable <<= pin;
disable <<= pin;
if (value == -1) {
gpio_output_set(0, 0, enable, disable);
} else {
gpio_output_set(value << pin, (1 - value) << pin, enable, disable);
}
}
IRAM NOINSTR static void rx_isr(void *param) {
/* TODO(alashkin): add errors checking */
unsigned int peri_reg = READ_PERI_REG(UART_INTR_STATUS(UART_MAIN));
static volatile int tail = 0;
(void) param;
if ((peri_reg & UART_RXBUF_FULL) != 0 || (peri_reg & UART_RX_NEW) != 0) {
int char_count, i;
CLEAR_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN),
UART_RXBUF_FULL | UART_RX_NEW);
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
char_count = READ_PERI_REG(UART_DATA_STATUS(UART_MAIN)) & 0x000000FF;
/* TODO(mkm): handle overrun */
for (i = 0; i < char_count; i++) {
char ch = READ_PERI_REG(UART_BUF(UART_MAIN)) & 0xFF;
if (s_custom_callback != NULL) {
s_custom_callback(ch);
} else {
rx_buf[tail] = ch;
if (rx_buf[tail] == UART_SIGINT_CHAR && uart_interrupt_cb) {
/* swallow the intr byte */
tail = (tail - 1) % RX_BUFFER_SIZE;
uart_interrupt_cb(UART_SIGINT_CHAR);
}
tail = (tail + 1) % RX_BUFFER_SIZE;
}
}
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
SET_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
if (s_custom_callback == NULL) {
#ifndef RTOS_SDK
system_os_post(TASK_PRIORITY, 0, tail);
#else
rtos_dispatch_char_handler(tail);
#endif
}
}
}
void esp_uart_print_status(void *arg) {
struct esp_uart_state *us = (struct esp_uart_state *) arg;
struct esp_uart_stats *s = &us->stats;
struct esp_uart_stats *ps = &us->prev_stats;
int uart_no = us->cfg->uart_no;
fprintf(
stderr,
"UART%d ints %u/%u/%u; rx en %d bytes %u buf %u fifo %u, ovf %u, lcs %u; "
"tx %u %u %u, thr %u; hf %u i 0x%03x ie 0x%03x cts %d\n",
uart_no, s->ints - ps->ints, s->rx_ints - ps->rx_ints,
s->tx_ints - ps->tx_ints, us->rx_enabled, s->rx_bytes - ps->rx_bytes,
us->rx_buf.used, rx_fifo_len(us->cfg->uart_no),
s->rx_overflows - ps->rx_overflows,
s->rx_linger_conts - ps->rx_linger_conts, s->tx_bytes - ps->tx_bytes,
us->tx_buf.used, tx_fifo_len(us->cfg->uart_no),
s->tx_throttles - ps->tx_throttles, system_get_free_heap_size(),
READ_PERI_REG(UART_INT_RAW(uart_no)),
READ_PERI_REG(UART_INT_ENA(uart_no)), cts(uart_no));
memcpy(ps, s, sizeof(*s));
}
static void hard_i2c_stop(void)
{
int count_ = 1000;
WRITE_PERI_REG(PREG_I2C_MS_TOKEN_LIST_REG0, ((I2C_END << 28) |
(I2C_END << 24) |
(I2C_END << 20) |
(I2C_END << 16) |
(I2C_END << 12) |
(I2C_END << 8) |
(I2C_END << 4) |
(I2C_STOP << 0) ));
// Toggle start low then high
WRITE_PERI_REG(PREG_I2C_MS_CTRL, ((READ_PERI_REG(PREG_I2C_MS_CTRL)) & 0xfffffffe ));
WRITE_PERI_REG(PREG_I2C_MS_CTRL, ((READ_PERI_REG(PREG_I2C_MS_CTRL)) | 0x1 ));
while( ((READ_PERI_REG(PREG_I2C_MS_CTRL)) & (1 << I2C_M_STATUS)) && (count_ -- )); // Wait for the transfer to complete
}
static uint32 get_gpio16()
{
// set output level to 1
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(1));
// read level
WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc)
| (uint32)0x1); // mux configuration for XPD_DCDC and
// rtc_gpio0 connection
WRITE_PERI_REG(RTC_GPIO_CONF,
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe)
| (uint32)0x0); // mux configuration for out enable
WRITE_PERI_REG(
RTC_GPIO_ENABLE, READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); // out disable
uint32 x = (READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
return x;
}
IRAM NOINSTR static void esp_handle_uart_int(struct esp_uart_state *us) {
const int uart_no = us->cfg->uart_no;
/* Since both UARTs use the same int, we need to apply the mask manually. */
const unsigned int int_st = READ_PERI_REG(UART_INT_ST(uart_no)) &
READ_PERI_REG(UART_INT_ENA(uart_no));
if (int_st == 0) return;
us->stats.ints++;
if (int_st & UART_RXFIFO_OVF_INT_ST) us->stats.rx_overflows++;
if (int_st & UART_CTS_CHG_INT_ST) {
if (cts(uart_no) != 0 && tx_fifo_len(uart_no) > 0) us->stats.tx_throttles++;
}
if (int_st & (UART_RX_INTS | UART_TX_INTS)) {
if (int_st & UART_RX_INTS) us->stats.rx_ints++;
if (int_st & UART_TX_INTS) us->stats.tx_ints++;
/* Wake up the processor and disable TX and RX ints until it runs. */
WRITE_PERI_REG(UART_INT_ENA(uart_no), UART_INFO_INTS);
us->cfg->dispatch_cb(uart_no);
}
WRITE_PERI_REG(UART_INT_CLR(uart_no), int_st);
}
int gdb_read_uart_buf(char *buf) {
unsigned int peri_reg = READ_PERI_REG(UART_INTR_STATUS(UART_MAIN));
if ((peri_reg & UART_RXBUF_FULL) != 0 || (peri_reg & UART_RX_NEW) != 0) {
int char_count, i;
CLEAR_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN),
UART_RXBUF_FULL | UART_RX_NEW);
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
char_count = READ_PERI_REG(UART_DATA_STATUS(UART_MAIN)) & 0x000000FF;
for (i = 0; i < char_count; i++) {
buf[i] = READ_PERI_REG(UART_BUF(UART_MAIN)) & 0xFF;
}
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
SET_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
return char_count;
}
return 0;
}
void mp_hal_pin_config_od(mp_hal_pin_obj_t pin_id) {
const pyb_pin_obj_t *pin = &pyb_pin_obj[pin_id];
if (pin->phys_port == 16) {
// configure GPIO16 as input with output register holding 0
WRITE_PERI_REG(PAD_XPD_DCDC_CONF, (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | 1);
WRITE_PERI_REG(RTC_GPIO_CONF, READ_PERI_REG(RTC_GPIO_CONF) & ~1);
WRITE_PERI_REG(RTC_GPIO_ENABLE, (READ_PERI_REG(RTC_GPIO_ENABLE) & ~1)); // input
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & ~1)); // out=0
return;
}
ETS_GPIO_INTR_DISABLE();
PIN_FUNC_SELECT(pin->periph, pin->func);
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin->phys_port)),
GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin->phys_port)))
| GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); // open drain
GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS,
GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << pin->phys_port));
ETS_GPIO_INTR_ENABLE();
}
static void rx_buff_read_done(void)
{
union sdio_slave_status sdio_sta;
/////modify sdio status reg
sdio_sta.word_value=READ_PERI_REG(SLC_HOST_CONF_W2);
sdio_sta.elm_value.comm_cnt++;
sdio_sta.elm_value.rd_empty=1;
sdio_sta.elm_value.rx_length=0;
sdio_sta.elm_value.intr_no &= (~RX_AVAILIBLE);
WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register
//os_printf("rx_buff_read_done\r\n");
}
/**
* Uniform way of getting GPIO input value. Handles GPIO 0-16.
* The pin must be initiated with easygpio_pinMode() so that the pin mux is setup as a gpio in the first place.
* If you know that you won't be using GPIO16 then you'd better off by just using GPIO_INPUT_GET().
*/
uint8_t
easygpio_inputGet(uint8_t gpio_pin) {
if (16==gpio_pin) {
return (READ_PERI_REG(RTC_GPIO_IN_DATA) & 1UL);
} else {
#ifdef EASYGPIO_USE_GPIO_INPUT_GET
return GPIO_INPUT_GET(GPIO_ID_PIN(gpio_pin));
#else
// this does *not* work, maybe GPIO_IN_ADDRESS is the wrong address
return ((GPIO_REG_READ(GPIO_IN_ADDRESS) > gpio_pin) & 1UL);
#endif
}
}
static void uartIsrHdl(void *arg)
{
char c;
char buf[50];
char *item;
int r;
size_t len;
BaseType_t xHigherPriorityTaskWoken;
SET_PERI_REG_MASK(UART_INT_CLR_REG(0), UART_RXFIFO_FULL_INT_CLR);
while (READ_PERI_REG(UART_STATUS_REG(0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
c = READ_PERI_REG(UART_FIFO_REG(0));
if (c == 'r') {
ets_printf("ISR r");
xRingbufferPrintInfo(rb);
item = xRingbufferReceiveFromISR(rb, &len);
if (item == NULL) {
ets_printf("ISR recv fail!\n");
} else if (len == 0) {
ets_printf("ISR recv NULL!\n");
vRingbufferReturnItemFromISR(rb, item, &xHigherPriorityTaskWoken);
} else {
ets_printf("ISR recv '%s' (%d bytes, %p)\n", buf, len, buf);
vRingbufferReturnItemFromISR(rb, item, &xHigherPriorityTaskWoken);
}
} else {
sprintf(buf, "UART: %c", c);
ets_printf("ISR w");
xRingbufferPrintInfo(rb);
r = xRingbufferSendFromISR(rb, buf, strlen(buf) + 1, &xHigherPriorityTaskWoken);
if (!r) {
ets_printf("ISR send fail\n");
}
}
}
if (xHigherPriorityTaskWoken) {
portYIELD_FROM_ISR();
}
}
IRAM bool adj_rx_fifo_full_thresh(struct mgos_uart_state *us) {
int uart_no = us->uart_no;
uint8_t thresh = us->cfg.dev.rx_fifo_full_thresh;
uint8_t rx_fifo_len = esp_uart_rx_fifo_len(uart_no);
if (rx_fifo_len >= thresh && us->cfg.rx_fc_type == MGOS_UART_FC_SW) {
thresh = us->cfg.dev.rx_fifo_fc_thresh;
}
if (get_rx_fifo_full_thresh(uart_no) != thresh) {
uint32_t conf1 = READ_PERI_REG(UART_CONF1(uart_no));
conf1 = (conf1 & ~0x7f) | thresh;
WRITE_PERI_REG(UART_CONF1(uart_no), conf1);
}
return (rx_fifo_len < thresh);
}
LOCAL void slc_isr(void) {
//portBASE_TYPE HPTaskAwoken=0;
struct sdio_queue *finishedDesc;
uint32 slc_intr_status;
int x;
slc_intr_status = READ_PERI_REG(SLC_INT_STATUS);
//clear all intr flags
WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);//slc_intr_status);
if ( (slc_intr_status & SLC_RX_EOF_INT_ST))
{
//The DMA subsystem is done with this block: Push it on the queue so it can be re-used.
finishedDesc=(struct sdio_queue*)READ_PERI_REG(SLC_RX_EOF_DES_ADDR);
curdma = (uint32_t*)finishedDesc->buf_ptr;
//Allow signal jamming, useful for testing output.
if( jam_color < 0 )
{
//*startdma = premodulated_table[0];
int lk = 0;
if( gline & 1 )
lk = (CbLookup[gline>>1]>>4)&0x0f;
else
static IRAM_ATTR void spi_intr(void *arg)
{
spi_host_t host;
uint32_t trans_done;
if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI0) { // DPORT_SPI_INT_STATUS_SPI0
trans_done = SPI0.slave.val & 0x1F;
SPI0.slave.val &= ~0x3FF;
host = CSPI_HOST;
} else if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI1) { // DPORT_SPI_INT_STATUS_SPI1
trans_done = SPI1.slave.val & 0x1F;
SPI1.slave.val &= ~0x1F;
host = HSPI_HOST;
} else {
return;
}
if (spi_object[host]) {
if (spi_object[host]->event_cb) {
spi_object[host]->event_cb(SPI_TRANS_DONE_EVENT, &trans_done);
}
}
}
/******************************************************************************
* FunctionName : uart_recvTask
* Description : system task triggered on receive interrupt, empties FIFO and calls callbacks
*******************************************************************************/
static void ICACHE_FLASH_ATTR
uart_recvTask(os_event_t *events)
{
while (READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
//WRITE_PERI_REG(0X60000914, 0x73); //WTD // commented out by TvE
// read a buffer-full from the uart
uint16 length = 0;
char buf[128];
while ((READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) &&
(length < 128)) {
buf[length++] = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF;
}
#ifdef UART_DBG
os_printf("%d ix %d\n", system_get_time(), length);
#endif
for (int i=0; i<MAX_CB; i++) {
if (uart_recv_cb[i] != NULL) (uart_recv_cb[i])(buf, length);
}
}
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR|UART_RXFIFO_TOUT_INT_CLR);
ETS_UART_INTR_ENABLE();
}
static void ICACHE_FLASH_ATTR recvTask(os_event_t *events)
{
uint8_t i;
while (READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S))
{
WRITE_PERI_REG(0X60000914, 0x73); //WTD
uint16 length = 0;
while ((READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) && (length<MAX_UARTBUFFER))
uartbuffer[length++] = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF;
for (i = 0; i < MAX_CONN; ++i)
if (connData[i].conn)
espbuffsent(&connData[i], uartbuffer, length);
}
if(UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_RXFIFO_FULL_INT_ST))
{
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
}
else if(UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_RXFIFO_TOUT_INT_ST))
{
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
}
ETS_UART_INTR_ENABLE();
}
void some_timerfunc(void *arg)
{
os_printf("Resetting ...\n");
// Pause to allow test to output before resetting
os_delay_us(1000);
// Reset by pulling reset GPIO (connected to reset) low
// XXX Only works for GPIO 16
WRITE_PERI_REG(RTC_GPIO_OUT,
(READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(0));
// No need to reschedule in case pin wasn't connected as we
// set up a timer to run forever
}
static void finishDma()
{
//No need to finish if no DMA transfer going on
if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) {
return;
}
//Wait till fifo done
while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ;
//Wait for last bytes to leave i2s xmit thing
//ToDo: poll bit in next hw
// for (i=0; i<(1<<8); i++);
while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE));
//Reset I2S for next transfer
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START | I2S_INLINK_START);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
// for (i=0; i<(1<<8); i++);
while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK));
}
/******************************************************************************
* FunctionName : uart0_rx_intr_handler
* Description : Internal used function
* UART0 interrupt handler, add self handle code inside
* Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg
* Returns : NONE
*******************************************************************************/
static void // must not use ICACHE_FLASH_ATTR !
uart0_rx_intr_handler(void *para)
{
// we assume that uart1 has interrupts disabled (it uses the same interrupt vector)
uint8 uart_no = UART0;
const uint32 one_sec = 1000000; // one second in usecs
// we end up largely ignoring framing errors and we just print a warning every second max
if (READ_PERI_REG(UART_INT_RAW(uart_no)) & UART_FRM_ERR_INT_RAW) {
uint32 now = system_get_time();
if (last_frm_err == 0 || (now - last_frm_err) > one_sec) {
#ifdef UART_DBG
os_printf("UART framing error (bad baud rate?)\n");
#endif
last_frm_err = now;
}
// clear rx fifo (apparently this is not optional at this point)
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST);
// reset framing error
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_FRM_ERR_INT_CLR);
// once framing errors are gone for 10 secs we forget about having seen them
} else if (last_frm_err != 0 && (system_get_time() - last_frm_err) > 10*one_sec) {
last_frm_err = 0;
}
if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)
|| UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST))
{
#ifdef UART_DBG
os_printf("stat:%02X",*(uint8 *)UART_INT_ENA(uart_no));
#endif
ETS_UART_INTR_DISABLE();
system_os_post(recvTaskPrio, 0, 0);
}
}
void ICACHE_FLASH_ATTR led_spi_master_16bit_write(uint8 spi_no, uint8_t lowFirstByte, uint8 highLastByte)
{
uint32 regvalue;
if (spi_no > 1)
{
return;
}
regvalue = 0xF0000000 | ((uint32) (highLastByte << 8) | lowFirstByte); //configure transmission variable,9bit transmission length and first 8 command bit
while (READ_PERI_REG(SPI_FLASH_CMD(spi_no)) & SPI_FLASH_USR)
; //waiting for spi module available
WRITE_PERI_REG(SPI_FLASH_USER2(spi_no), regvalue); //write command and command length into spi reg
SET_PERI_REG_MASK(SPI_FLASH_CMD(spi_no), SPI_FLASH_USR); //transmission start
}
static void ICACHE_FLASH_ATTR user_rx_task(os_event_t *events) {
if(events->sig == 0){
uint8 fifo_len = (READ_PERI_REG(UART_STATUS(UART0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
uint8 d_tmp = 0;
uint8 idx=0;
for(idx=0;idx<fifo_len;idx++) {
d_tmp = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF;
uart_tx_one_char(UART0, d_tmp);
if( has_space() ) {
serial_buffer[putpos++ & POS_MASK] = d_tmp;
}
}
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR|UART_RXFIFO_TOUT_INT_CLR);
uart_rx_intr_enable(UART0);
if( serial_datalen() && user_rx_callback ) {
user_rx_callback(serial_datalen());
}
}
void gpio_intr_process(void)
{
uint32 intr_status;
int intr_num;
uint8 gpio_num;
intr_status = READ_PERI_REG(PCNT_INT_ST);
while ((intr_num = __builtin_ctz(intr_status)) >= 0) {
intr_status &= ~BIT(intr_num);
gpio_num = intr_gpio_nums[intr_num];
gpio_intr_clear(intr_num);
switch (gpio_num) {
default:
printf("gpio %d intr come\n", gpio_num);
break;
}
}
}
static void tx_buff_handle_done(void)
{
union sdio_slave_status sdio_sta;
/////config tx queue information
tx_que.blocksize=TX_BUFFER_SIZE;
tx_que.datalen=0;
tx_que.eof=0;
tx_que.owner=1;
/////modify sdio status reg
sdio_sta.word_value=READ_PERI_REG(SLC_HOST_CONF_W2);
sdio_sta.elm_value.wr_busy=0;
sdio_sta.elm_value.intr_no |= TX_AVAILIBLE;
SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START); //tx buffer is ready for being written
WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register
//*******************************************************************//
}
void
UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
{
uint32 reg_val = 0;
UART_ClearIntrStatus(uart_no, UART_INTR_MASK);
reg_val = READ_PERI_REG(UART_CONF1(uart_no)) & ~((UART_RX_FLOW_THRHD << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN) ;
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_TOUT_INT_ENA) ?
((((pUARTIntrConf->UART_RX_TimeOutIntrThresh)&UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S) | UART_RX_TOUT_EN) : 0);
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_FULL_INT_ENA) ?
(((pUARTIntrConf->UART_RX_FifoFullIntrThresh)&UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) : 0);
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_TXFIFO_EMPTY_INT_ENA) ?
(((pUARTIntrConf->UART_TX_FifoEmptyIntrThresh)&UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S) : 0);
WRITE_PERI_REG(UART_CONF1(uart_no), reg_val);
CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_INTR_MASK);
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
}
/**
* @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS).
*
*/
void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
{
if (spiNum > SpiNum_HSPI) {
return;
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
// 8bits cmd, 0x04 is eps8266 slave write cmd value
WRITE_PERI_REG(SPI_USER2(spiNum),
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
| MASTER_WRITE_STATUS_TO_SLAVE_CMD);
// Set data send buffer length.
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S);
WRITE_PERI_REG(SPI_W0(spiNum), (uint32)(data));
// Start SPI
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
}
static void lcdIfaceInit()
{
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S));
// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX<<GPIO_GPIO_FUNC0_OUT_SEL_S));
//GPIO_SET_GPIO_FUNC11_OUT_INV_SEL(1); //old
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC11_OUT_INV_SEL);
//Reset I2S subsystem
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
WRITE_PERI_REG(I2S_CONF_REG(0), 0);//I2S_SIG_LOOPBACK);
WRITE_PERI_REG(I2S_CONF2_REG(0), 0);
WRITE_PERI_REG(I2S_SAMPLE_RATE_CONF_REG(0),
(16 << I2S_RX_BITS_MOD_S) |
(16 << I2S_TX_BITS_MOD_S) |
(1 << I2S_RX_BCK_DIV_NUM_S) |
(1 << I2S_TX_BCK_DIV_NUM_S));
WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
I2S_CLKA_ENA | I2S_CLK_EN |
(1 << I2S_CLKM_DIV_A_S) |
(1 << I2S_CLKM_DIV_B_S) |
(1 << I2S_CLKM_DIV_NUM_S));
WRITE_PERI_REG(I2S_FIFO_CONF_REG(0),
(32 << I2S_TX_DATA_NUM_S) | //Low watermark for IRQ
(32 << I2S_RX_DATA_NUM_S));
WRITE_PERI_REG(I2S_CONF1_REG(0), I2S_RX_PCM_BYPASS | I2S_TX_PCM_BYPASS);
WRITE_PERI_REG(I2S_CONF_CHAN_REG(0), (2 << I2S_TX_CHAN_MOD_S) | (2 << I2S_RX_CHAN_MOD_S));
//Invert WS to active-low
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RIGHT_FIRST | I2S_RX_RIGHT_FIRST);
WRITE_PERI_REG(I2S_TIMING_REG(0), 0);
}
irom static bool rtcgpio_input_get(void)
{
return(!!(READ_PERI_REG(RTC_GPIO_IN_DATA) & 0x01));
}
IRAM static int rx_byte(int uart_no) {
return READ_PERI_REG(UART_FIFO(uart_no)) & 0xff;
}
IRAM int esp_uart_rx_fifo_len(int uart_no) {
return READ_PERI_REG(UART_STATUS(uart_no)) & 0xff;
}
/* Active for CTS is 0, i.e. 0 = ok to send. */
IRAM int esp_uart_cts(int uart_no) {
return (READ_PERI_REG(UART_STATUS(uart_no)) & UART_CTSN) ? 1 : 0;
}
