PVRSRV_ERROR PVRSRVRGXEnableBreakpointKM(PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_HANDLE hMemCtxPrivData)
{
DEVMEM_MEMDESC *psFWMemContextMemDesc = RGXGetFWMemDescFromMemoryContextHandle(hMemCtxPrivData);
PVRSRV_ERROR eError = PVRSRV_OK;
RGXFWIF_KCCB_CMD sBPCmd;
RGXFWIF_DM eDataMaster = psDeviceNode->psDevConfig->eBPDM;
if (psDeviceNode->psDevConfig->bBPSet == IMG_FALSE)
return PVRSRV_ERROR_BP_NOT_SET;
sBPCmd.eCmdType = RGXFWIF_KCCB_CMD_BP;
sBPCmd.uCmdData.sBPData.bEnable = IMG_TRUE;
sBPCmd.uCmdData.sBPData.ui32Flags = RGXFWIF_BPDATA_FLAGS_CTL;
RGXSetFirmwareAddress(&sBPCmd.uCmdData.sBPData.psFWMemContext,
psFWMemContextMemDesc,
0 ,
RFW_FWADDR_NOREF_FLAG | RFW_FWADDR_METACACHED_FLAG);
eError = RGXScheduleCommand(psDeviceNode->pvDevice,
eDataMaster,
&sBPCmd,
sizeof(sBPCmd),
IMG_TRUE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVRGXEnableBreakpointKM: RGXScheduleCommand failed. Error:%u", eError));
return eError;
}
/* Wait for FW to complete */
eError = RGXWaitForFWOp(psDeviceNode->pvDevice, eDataMaster, psDeviceNode->psSyncPrim, IMG_TRUE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVRGXEnableBreakpointKM: Wait for completion aborted with error (%u)", eError));
return eError;
}
return eError;
}
PVRSRV_ERROR RGXSLCCacheInvalidateRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
PMR *psPmr)
{
RGXFWIF_KCCB_CMD sFlushInvalCmd;
IMG_UINT32 ulPMRFlags;
IMG_UINT32 ui32DeviceCacheFlags;
PVRSRV_ERROR eError = PVRSRV_OK;
PVR_ASSERT(psDeviceNode);
/* In DEINIT state, we stop scheduling SLC flush commands, because we don't know in what state the firmware is.
* Anyway, if we are in DEINIT state, we don't care anymore about FW memory consistency
*/
if (psDeviceNode->eDevState != PVRSRV_DEVICE_STATE_DEINIT)
{
/* get the PMR's caching flags */
eError = PMR_Flags(psPmr, &ulPMRFlags);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_WARNING, "RGXSLCCacheInvalidateRequest: Unable to get the caching attributes of PMR %p",psPmr));
}
ui32DeviceCacheFlags = DevmemDeviceCacheMode(ulPMRFlags);
/* Schedule a SLC flush and invalidate if
* - the memory is cached.
* - we can't get the caching attributes (by precaution).
*/
if ((ui32DeviceCacheFlags == PVRSRV_MEMALLOCFLAG_GPU_CACHED) || (eError != PVRSRV_OK))
{
/* Schedule the SLC flush command ... */
#if defined(PDUMP)
PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "Submit SLC flush and invalidate");
#endif
sFlushInvalCmd.eCmdType = RGXFWIF_KCCB_CMD_SLCFLUSHINVAL;
sFlushInvalCmd.uCmdData.sSLCFlushInvalData.bInval = IMG_TRUE;
sFlushInvalCmd.uCmdData.sSLCFlushInvalData.bDMContext = IMG_FALSE;
sFlushInvalCmd.uCmdData.sSLCFlushInvalData.eDM = 0;
sFlushInvalCmd.uCmdData.sSLCFlushInvalData.psContext.ui32Addr = 0;
eError = RGXSendCommandWithPowLock(psDeviceNode->pvDevice,
RGXFWIF_DM_GP,
&sFlushInvalCmd,
sizeof(sFlushInvalCmd),
IMG_TRUE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"RGXSLCCacheInvalidateRequest: Failed to schedule SLC flush command with error (%u)", eError));
}
else
{
/* Wait for the SLC flush to complete */
eError = RGXWaitForFWOp(psDeviceNode->pvDevice, RGXFWIF_DM_GP, psDeviceNode->psSyncPrim, IMG_TRUE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"RGXSLCCacheInvalidateRequest: SLC flush and invalidate aborted with error (%u)", eError));
}
}
}
}
return eError;
}
