void bootblock_mainboard_early_init(void)
{
/* Let gpio2ab io domains works at 1.8V.
*
* If io_vsel[0] == 0(default value), gpio2ab io domains is 3.0V
* powerd by APIO2_VDD, otherwise, 1.8V supplied by APIO2_VDDPST.
* But from the schematic of kevin rev0, the APIO2_VDD and
* APIO2_VDDPST both are 1.8V(intentionally?).
*
* So, by default, CPU1_SDIO_PWREN(GPIO2_A2) can't output 3.0V
* because the supply is 1.8V.
* Let ask GPIO2_A2 output 1.8V to make GPIO interal logic happy.
*/
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));
/*
* Let's enable these power rails here, we are already running the SPI
* Flash based code.
*/
gpio_output(GPIO(0, B, 2), 1); /* PP1500_EN */
gpio_output(GPIO(0, B, 4), 1); /* PP3000_EN */
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
"CONSOLE_SERIAL_UART should be UART2");
/* iomux: select gpio4c[4:3] as uart2 dbg port */
write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
/* grf soc_con7[11:10] use for uart2 select */
write32(&rk3399_grf->soc_con7, UART2C_SEL);
}
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 0:
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(1, 1); /* VCC33_LCD */
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
uint32_t data_size)
{
if (hash_alg != VB2_HASH_SHA256) {
printk(BIOS_INFO, "RK3288 doesn't support hash_alg %d!\n",
hash_alg);
return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
}
write32(&crypto->ctrl, RK_SETBITS(1 << 6)); /* Assert HASH_FLUSH */
udelay(1); /* for 10+ cycles to */
write32(&crypto->ctrl, RK_CLRBITS(1 << 6)); /* clear out old hash */
/* Enable DMA byte swapping for little-endian bus (Byteswap_??FIFO) */
write32(&crypto->conf, 1 << 5 | 1 << 4 | 1 << 3);
write32(&crypto->intena, HRDMA_ERR | HRDMA_DONE); /* enable interrupt */
write32(&crypto->hash_msg_len, data_size); /* program total size */
write32(&crypto->hash_ctrl, 1 << 3 | 0x2); /* swap DOUT, SHA256 */
printk(BIOS_DEBUG, "Initialized RK3288 HW crypto for %u byte SHA256\n",
data_size);
return VB2_SUCCESS;
}
static void configure_i2s(void)
{
write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
/* AUDIO IO domain 1.8V voltage selection */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
rk808_configure_switch(1, 1); /* VCC33_LCD */
}
static void configure_vop(void)
{
writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
/* lcdc(vop) iodomain select 1.8V */
writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
}
static void configure_codec(void)
{
write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
i2c_init(2, 400000); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
/*
* BL_EN gates VCC_LCD. This might be changed in future revisions
* of the board so that the display can be stablized before we
* turn on the backlight.
*
* To minimize display corruption, turn off LCDC_BL before
* powering on the backlight.
*/
switch (board_id()) {
case 0:
gpio_output(GPIO(7, A, 3), 1);
break;
default:
gpio_output(GPIO(7, A, 2), 1);
break;
}
gpio_output(GPIO_LCDC_BL, 0);
rk808_configure_switch(1, 1); /* VCC33_LCD */
/* EDP_HPD setup */
switch (board_id()) {
case 0:
/* not present */
break;
default:
/* Unlike other Veyrons, Danger has external pull resistors on
* EDP_HPD. Default for GPIO(7, B, 3) is pull-down, set to
* float.
*/
gpio_input(GPIO(7, B, 3));
write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
static void configure_vop(void)
{
writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
/* lcdc(vop) iodomain select 1.8V */
writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 4, 1800); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 6, 1000); /* VCC10_LCD */
gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */
break;
default:
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
break;
}
}
int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
{
uint32_t intsts;
write32(&crypto->intsts, HRDMA_ERR | HRDMA_DONE); /* clear interrupts */
/* NOTE: This assumes that the DMA is reading from uncached SRAM. */
write32(&crypto->hrdmas, (uint32_t)buf);
write32(&crypto->hrdmal, size / sizeof(uint32_t));
write32(&crypto->ctrl, RK_SETBITS(1 << 3)); /* Set HASH_START */
do {
intsts = read32(&crypto->intsts);
if (intsts & HRDMA_ERR) {
printk(BIOS_ERR, "ERROR: DMA error during HW crypto\n");
return VB2_ERROR_UNKNOWN;
}
} while (!(intsts & HRDMA_DONE)); /* wait for DMA to finish */
return VB2_SUCCESS;
}
void rk_display_init(device_t dev, u32 lcdbase,
unsigned long fb_size)
{
struct edid edid;
uint32_t val;
struct soc_rockchip_rk3288_config *conf = dev->chip_info;
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase));
memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
switch (conf->vop_mode) {
case VOP_MODE_NONE:
return;
case VOP_MODE_AUTO_DETECT:
/* try EDP first, then HDMI */
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
rkclk_configure_edp();
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
/* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4));
/* select epd signal from vop0 or vop1 */
val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) :
RK_CLRBITS(1 << 5);
write32(&rk3288_grf->soc_con6, val);
rk_edp_init();
if (rk_edp_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_EDP;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from EDP.\n");
if (conf->vop_mode == VOP_MODE_EDP)
return;
}
/* fall thru */
case VOP_MODE_HDMI:
printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n");
rkclk_configure_hdmi();
rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz);
rk_hdmi_init(conf->vop_id);
if (rk_hdmi_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_HDMI;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n");
if (conf->vop_mode == VOP_MODE_HDMI)
return;
}
/* fall thru */
default:
printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n");
return;
}
if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) {
printk(BIOS_WARNING, "config vop err\n");
return;
}
edid_set_framebuffer_bits_per_pixel(&edid,
conf->framebuffer_bits_per_pixel, 0);
rkvop_mode_set(conf->vop_id, &edid, detected_mode);
rkvop_prepare(conf->vop_id, &edid);
rkvop_enable(conf->vop_id, lcdbase);
switch (detected_mode) {
case VOP_MODE_HDMI:
if (rk_hdmi_enable(&edid)) {
printk(BIOS_WARNING, "hdmi enable err\n");
return;
}
/*
* HACK: if we do remove this delay, HDMI TV may not show
* anythings. So we make an delay here, ensure TV have
* enough time to respond.
*/
mdelay(2000);
break;
case VOP_MODE_EDP:
default:
if (rk_edp_prepare()) {
printk(BIOS_WARNING, "edp prepare err\n");
return;
}
if (rk_edp_enable()) {
printk(BIOS_WARNING, "edp enable err\n");
return;
}
mainboard_power_on_backlight();
break;
}
set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
}
