void InitialiseDisplayTFT(void) { /* Enable peripherals */ ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); SysCtlDelay(100); /* Set command and reset pin as outputs */ ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, TFT_RESET_PIN | TFT_COMMAND_PIN); /* Enable CS pin as output */ ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_5); /* Enable pin PB7 for SSI2 SSI2TX */ ROM_GPIOPinConfigure(GPIO_PB7_SSI2TX); ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_7); /* Enable pin PB6 for SSI2 SSI2RX */ ROM_GPIOPinConfigure(GPIO_PB6_SSI2RX); ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_6); /* Enable pin PB4 for SSI2 SSI2CLK */ ROM_GPIOPinConfigure(GPIO_PB4_SSI2CLK); ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4); /* Configure the SSI2 port to run at 15.0MHz */ ROM_SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 15000000, 8); ROM_SSIEnable(SSI2_BASE); /* Reset the display */ TFT_RESET_HIGH; my_delay_tft(100); TFT_RESET_LOW; my_delay_tft(100); TFT_RESET_HIGH; my_delay_tft(100); /* Send command sequence */ init_sequence_tft(); cursor_y = cursor_x = 0; textcolor = 0xFFFF; textbgcolor = 0x0000; wrap = 1; }
/* Init_sdcard * * Initialise FatFS and SD Card */ void sdcard_init(void) { // Enable SSI0 for the SD Card ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); // Configure Pins ROM_GPIOPinConfigure(GPIO_PA4_SSI0RX); ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_4); ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK); ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2); ROM_GPIOPinConfigure(GPIO_PA3_SSI0FSS); ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); ROM_GPIOPinConfigure(GPIO_PA5_SSI0TX); ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5); FRESULT fres = f_mount(0, &fs); if (fres != (FRESULT)FR_OK) { UARTprintf("f_mount result: %d\r\n", fres); } configure_playback(); }
void enableSPI(unsigned short SPINum, unsigned short wordLength, unsigned long dataRate) { ROM_SysCtlPeripheralEnable(SysCtlSSI[SPINum]); ROM_SysCtlPeripheralSleepEnable(SysCtlSSI[SPINum]); ROM_SysCtlPeripheralEnable(GPIO[ SPIPins[SPINum][0]/8 ]); int i; for (i = 0; i < 4; i++){ ROM_GPIOPinTypeSSI(GPIO[ SPIPins[SPINum][i]/8 ], bit8[ SPIPins[SPINum][i]%8 ]); ROM_GPIOPinConfigure(SPIPins[SPINum][i + 4]); } // Polarity 0, Phase 0 ROM_SSIConfigSetExpClk(SSIBase[SPINum], SysCtlClockGet(), 0, SSI_MODE_MASTER, dataRate, wordLength); SSIEnable(SSI_BASE); }
void pdlibSPI_ConfigureSPIInterface(unsigned char ucSSI) { g_SSI = ucSSI; #ifdef PART_LM4F120H5QR if(g_SSI < 6) { /* Enable clock for SSI */ ROM_SysCtlPeripheralEnable(g_SSIModule[ucSSI][SSIPERIPH]); /* Disable SSI module */ ROM_SSIDisable(g_SSIModule[ucSSI][SSIBASE]); /* Enable Clock for GPIO port used */ ROM_SysCtlPeripheralEnable(g_GPIOConfigure[ucSSI][GPIOPERIPH]); /* Configure GPIO pins */ ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSICLK]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSIFSS]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSIRX]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSITX]); ROM_GPIOPinTypeSSI(g_GPIOConfigure[ucSSI][GPIOBASE], g_GPIOConfigure[ucSSI][GPIOPINS]); /* Configure SSI */ ROM_SSIClockSourceSet(g_SSIModule[ucSSI][SSIBASE], SSI_CLOCK_SYSTEM); ROM_SSIConfigSetExpClk(g_SSIModule[ucSSI][SSIBASE], SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 500000, 8); ROM_SSIEnable(g_SSIModule[ucSSI][SSIBASE]); /* Clear initial data */ while(ROM_SSIDataGetNonBlocking(g_SSIModule[ucSSI][SSIBASE], (unsigned long*)&g_plRxData[0])); /* HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CPSR) = 8; HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CR0) &= ~(SSI_CR0_SPO | SSI_CR0_SPH); HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CR0) |= 0x00; */ } #endif }
void SPIClass::begin(uint8_t ssPin) { unsigned long initialData = 0; if(SSIModule == NOT_ACTIVE) { SSIModule = BOOST_PACK_SPI; } ROM_SysCtlPeripheralEnable(g_ulSSIPeriph[SSIModule]); ROM_SSIDisable(SSIBASE); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][0]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][1]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][2]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][3]); ROM_GPIOPinTypeSSI(g_ulSSIPort[SSIModule], g_ulSSIPins[SSIModule]); /* Polarity Phase Mode 0 0 SSI_FRF_MOTO_MODE_0 0 1 SSI_FRF_MOTO_MODE_1 1 0 SSI_FRF_MOTO_MODE_2 1 1 SSI_FRF_MOTO_MODE_3 */ slaveSelect = ssPin; pinMode(slaveSelect, OUTPUT); /* * Default to * System Clock, SPI_MODE_0, MASTER, * 4MHz bit rate, and 8 bit data */ ROM_SSIClockSourceSet(SSIBASE, SSI_CLOCK_SYSTEM); ROM_SSIConfigSetExpClk(SSIBASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 4000000, 8); ROM_SSIEnable(SSIBASE); //clear out any initial data that might be present in the RX FIFO while(ROM_SSIDataGetNonBlocking(SSIBASE, &initialData)); }
void SSI3DMASlaveClass::configureSSI3() { // // Enable the SSI3 Peripheral. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI3); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); // Configure GPIO Pins for SSI3 mode. // ROM_GPIOPinConfigure(GPIO_PQ0_SSI3CLK); ROM_GPIOPinConfigure(GPIO_PQ1_SSI3FSS); ROM_GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0); ROM_GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1); ROM_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0); ROM_SSIConfigSetExpClk(SSI3_BASE, F_CPU, SSI_FRF_MOTO_MODE_0, SSI_MODE_SLAVE, SPI_CLOCK / 12, 8); ROM_SSIEnable(SSI3_BASE); ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_RX | SSI_DMA_TX); }
void muxInit(void) { // enable SSI3 and GPIOD peripherals ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); // Configure GPIO pins for special functions GPIOPinConfigure(GPIO_PF2_SSI1CLK); GPIOPinConfigure(GPIO_PF1_SSI1TX); GPIOPinConfigure(GPIO_PF3_SSI1FSS); ROM_GPIOPinTypeSSI(MUX_BASE, DIN_PIN | SCLK_PIN | SYNC_PIN); //Configure and enable SSI port // Use internal 16Mhz RC oscillator as SSI clock source ROM_SSIClockSourceSet(SSI1_BASE, SSI_CLOCK_PIOSC); ROM_SSIConfigSetExpClk(SSI1_BASE, 16000000, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 8000000, 8); ROM_SSIEnable(SSI1_BASE); // Load default configuration parameters ROM_SSIDataPut(SSI1_BASE, ALL_OFF); }