static int dw_mci_init(u32 regbase, int bus_width, int index, int max_clock) { struct dwmci_host *host = NULL; int fifo_size = 0x20; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; } dw_mci_set_clk(index, max_clock * 2); host->name = NXP_NAME; host->ioaddr = (void *)regbase; host->buswidth = bus_width; host->clksel = dw_mci_clksel; host->dev_index = index; host->get_mmc_clk = dw_mci_get_clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | TX_WMARK(fifo_size/2); add_dwmci(host, max_clock, 400000); return 0; }
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host; unsigned long clk = cm_get_mmc_controller_clk_hz(); if (clk == 0) { printf("%s: MMC clock is zero!", __func__); return -EINVAL; } /* calloc for zero init */ host = calloc(1, sizeof(struct dwmci_host)); if (!host) { printf("%s: calloc() failed!\n", __func__); return -ENOMEM; } host->name = "SOCFPGA DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width; host->clksel = socfpga_dwmci_clksel; host->dev_index = index; /* fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); return add_dwmci(host, host->bus_hz, 400000); }
static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 fifo_size, fifoth_val; dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); return -1; } dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0); dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); fifo_size = dwmci_readl(host, DWMCI_FIFOTH); if (host->fifoth_val) fifoth_val = host->fifoth_val; else fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | TX_WMARK(fifo_size/2); dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); return 0; }
static int rockchip_dwmmc_probe(struct udevice *dev) { struct rockchip_mmc_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; int ret; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; host->name = dev->name; host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); host->buswidth = dtplat->bus_width; host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; priv->fifo_mode = 0; priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #else ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; #endif host->fifoth_val = MSIZE(0x2) | RX_WMARK(priv->fifo_depth / 2 - 1) | TX_WMARK(priv->fifo_depth / 2); host->fifo_mode = priv->fifo_mode; #ifdef CONFIG_PWRSEQ /* Enable power if needed */ ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", &pwr_dev); if (!ret) { ret = pwrseq_set_power(pwr_dev, true); if (ret) return ret; } #endif dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); host->mmc = &plat->mmc; host->mmc->priv = &priv->host; host->mmc->dev = dev; upriv->mmc = host->mmc; return dwmci_probe(dev); }
static int rockchip_dwmmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; u32 minmax[2]; int ret; int fifo_depth; ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; priv->periph = ret; if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock-freq-min-max", minmax, 2)) return -EINVAL; fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "fifo-depth", 0); if (fifo_depth < 0) return -EINVAL; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) host->fifo_mode = true; #ifdef CONFIG_PWRSEQ /* Enable power if needed */ ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", &pwr_dev); if (!ret) { ret = pwrseq_set_power(pwr_dev, true); if (ret) return ret; } #endif ret = add_dwmci(host, minmax[1], minmax[0]); if (ret) return ret; upriv->mmc = host->mmc; return 0; }
static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) { /* FIXME: probe from DT eventually too/ */ const unsigned long clk = cm_get_mmc_controller_clk_hz(); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; int fifo_depth; if (clk == 0) { printf("DWMMC: MMC clock is zero!"); return -EINVAL; } fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "fifo-depth", 0); if (fifo_depth < 0) { printf("DWMMC: Can't get FIFO depth\n"); return -EINVAL; } host->name = dev->name; host->ioaddr = (void *)dev_get_addr(dev); host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 4); host->clksel = socfpga_dwmci_clksel; /* * TODO([email protected]): Remove the need for this hack. * We only have one dwmmc block on gen5 SoCFPGA. */ host->dev_index = 0; /* Fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "drvsel", 3); priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "smplsel", 0); host->priv = priv; return 0; }
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host = NULL; host = calloc(sizeof(struct dwmci_host), 1); if (!host) { printf("dwmci_host calloc fail!\n"); return -1; } host->name = SOCFPGA_NAME; host->ioaddr = (void *)regbase; host->buswidth = bus_width; host->clksel = socfpga_dwmci_clksel; host->dev_index = index; /* fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ; host->fifoth_val = MSIZE(0x2) | RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); return add_dwmci(host, host->bus_hz, 400000); }
static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) { /* FIXME: probe from DT eventually too/ */ const unsigned long clk = cm_get_mmc_controller_clk_hz(); struct dwmci_host *host; struct dwmci_socfpga_priv_data *priv; fdt_addr_t reg_base; int bus_width, fifo_depth; if (clk == 0) { printf("DWMMC%d: MMC clock is zero!", idx); return -EINVAL; } /* Get the register address from the device node */ reg_base = fdtdec_get_addr(blob, node, "reg"); if (!reg_base) { printf("DWMMC%d: Can't get base address\n", idx); return -EINVAL; } /* Get the bus width from the device node */ bus_width = fdtdec_get_int(blob, node, "bus-width", 0); if (bus_width <= 0) { printf("DWMMC%d: Can't get bus-width\n", idx); return -EINVAL; } fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); if (fifo_depth < 0) { printf("DWMMC%d: Can't get FIFO depth\n", idx); return -EINVAL; } /* Allocate the host */ host = calloc(1, sizeof(*host)); if (!host) return -ENOMEM; /* Allocate the priv */ priv = calloc(1, sizeof(*priv)); if (!priv) { free(host); return -ENOMEM; } host->name = "SOCFPGA DWMMC"; host->ioaddr = (void *)reg_base; host->buswidth = bus_width; host->clksel = socfpga_dwmci_clksel; host->dev_index = idx; /* Fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3); priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0); host->priv = priv; return add_dwmci(host, host->bus_hz, 400000); }