status_t
FDILink::Train(display_mode* target)
{
CALLED();
uint32 bitsPerPixel;
switch (target->space) {
case B_RGB32_LITTLE:
bitsPerPixel = 32;
break;
case B_RGB16_LITTLE:
bitsPerPixel = 16;
break;
case B_RGB15_LITTLE:
bitsPerPixel = 15;
break;
case B_CMAP8:
default:
bitsPerPixel = 8;
break;
}
// Khz / 10. ( each output octet encoded as 10 bits.
uint32 linkBandwidth = gInfo->shared_info->fdi_link_frequency * 1000 / 10;
uint32 bps = target->timing.pixel_clock * bitsPerPixel * 21 / 20;
uint32 lanes = bps / (linkBandwidth * 8);
TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, lanes);
// Enable FDI clocks
Receiver().EnablePLL(lanes);
Receiver().SwitchClock(true);
Transmitter().EnablePLL(lanes);
status_t result = B_ERROR;
// TODO: Only _AutoTrain on IVYB Stepping B or later
// otherwise, _ManualTrain
if (gInfo->shared_info->device_type.Generation() >= 7)
result = _AutoTrain(lanes);
else if (gInfo->shared_info->device_type.Generation() == 6)
result = _SnbTrain(lanes);
else if (gInfo->shared_info->device_type.Generation() == 5)
result = _IlkTrain(lanes);
else
result = _NormalTrain(lanes);
if (result != B_OK) {
ERROR("%s: FDI training fault.\n", __func__);
}
return result;
}
Event* RetransmissionProtocol::Send(double senderTime, int sN, int length) {
if (sN >= 0) {
// Sending frame to channel has delay
double propagationDelay = senderTime + (double)length/(double)transmissionRate;
int rSeqNum = INT_MIN;
int status = 0;
//Forward Channel
status = Channel(length, propagationDelay);
// If loss receiver doesnt get called
if (status != LOSS)
rSeqNum = Receiver(propagationDelay, sN, status);
if (rSeqNum >= 0) {
// Reverse Channel
status = Channel(frameHeaderLength, propagationDelay);
//Sending ack to channel has delay
propagationDelay += (double)frameHeaderLength/(double)transmissionRate;
// If loss no event gets created
if (status != LOSS)
return CreateEvent(ACK, propagationDelay, status, rSeqNum);
}
}
return NULL;
}
int main(void)
{
WDTCTL = WDTPW | WDTHOLD;
P1DIR |= BIT0;
P1OUT &= ~BIT0;
// Test: initialize the CC1101 physical information structure. Once this is
// initialized, regular operation may begin.
CC1101SpiInit(&gPhyInfo, &gSpi, NULL);
CC1101GdoInit(&gPhyInfo, gGdo);
// Test: configure with default settings.
CC1101Configure(&gPhyInfo, &gCC1101Settings);
// Test: set the PA table to an initial power level.
CC1101WriteRegisters(&gPhyInfo, CC1101_PATABLE, gPaTable, 8);
// ---------------------------------------------------------------------------
/**
* Test polling transmit/receive operations on two different units. One unit
* is designated the receiver while the other is the transmitter. This method
* can be modified to use an interrupt-driven approach. Toggle an LED when
* done receiving and transmitting.
*/
#if defined(TEST_CC1101_RECEIVER)
Receiver();
#elif defined(TEST_CC1101_TRANSMITTER)
Transmitter();
#endif
return 0;
}
int
DOwner::start_receiver(const ACE_INET_Addr & local)
{
ACE_GUARD_RETURN (ACE_SYNCH_RECURSIVE_MUTEX, monitor, this->lock_, 0);
if (this->connections_ >= MAX_CONNECTIONS || flg_cancel_ != 0)
return -1;
for (u_int i = 0; i < MAX_CONNECTIONS; ++i)
{
if (this->list_connections_ [i] == 0)
{
ACE_NEW_RETURN (this->list_connections_[i],
Receiver (*this, i),
-1);
this->list_connections_[i]->open(local,
ACE_INET_Addr((u_short)0));
return 0;
}
}
ACE_ASSERT(0);
return -1;
}
/*---------------------------------------------------------------------------*/
int main(int count, char *strings[])
{ const int on=1;
int sd, port;
struct sockaddr_in addr;
char buffer[1024];
/*---Get parameters---*/
if ( count < 3 || count > 4)
{
printf("usage: %s [<listening-port>] <dest-addr> <dest-port>\n", strings[0]);
return 0;
}
if ( count == 4 )
{
port = atoi(strings[1]);
strings++;
}
else
port = DEFAULT_PORT;
/*---Create and configure socket---*/
sd = socket(PF_INET, SOCK_DGRAM, 0);
if ( sd < 0 )
panic("socket failed");
if ( setsockopt(sd, SOL_SOCKET, SO_BROADCAST, &on, sizeof(on)) != 0 )
panic("set broadcast failed");
bzero(&addr, sizeof(addr));
addr.sin_family = AF_INET;
addr.sin_port = htons(port);
if ( inet_aton("128.1.1.1", &addr.sin_addr) == 0 )
panic("inet_aton failed (%s)", strings[1]);
if ( bind(sd, (struct sockaddr*)&addr, sizeof(addr)) != 0 )
panic("bind failed");
addr.sin_port = htons(atoi(strings[2]));
if ( inet_aton(strings[1], &addr.sin_addr) == 0 )
panic("inet_aton failed (%s)", strings[1]);
/*---Create child---*/
if ( fork() )
Receiver(sd);
else
shutdown(sd, 0); /* close the input channel */
/*---Begin broadcast---*/
do
{
fgets(buffer, sizeof(buffer), stdin);
strtrim(buffer);
if ( sendto(sd, buffer, strlen(buffer)+1, 0, (struct sockaddr*)&addr, sizeof(addr)) < 0 )
perror("sendto");
}
while ( strcmp(buffer, "bye") != 0 );
/*---Wait for child termination & cleanup---*/
wait(0);
close(sd);
return 0;
}
int
Acceptor::make_svc_handler (Receiver *&sh)
{
ACE_Guard<ACE_Recursive_Thread_Mutex> locker (this->mutex_);
if (sessions_ >= MAX_RECEIVERS)
return -1;
for (size_t i = 0; i < MAX_RECEIVERS; ++i)
if (this->list_receivers_ [i] == 0)
{
ACE_NEW_RETURN (sh,
Receiver (this , i),
-1);
return 0;
}
return -1;
}
Receiver *
Acceptor::make_handler (void)
{
if (this->sessions_ >= RECEIVERS)
return 0;
for (int i = 0; i < RECEIVERS; ++i)
{
if (this->list_receivers_[i] == 0)
{
ACE_NEW_RETURN (this->list_receivers_[i],
Receiver (this, i),
0);
return this->list_receivers_[i];
}
}
return 0;
}
//-----------------------------------------------------
//
// MAIN
//
//-----------------------------------------------------
int
main(int argc, char *argv[])
{
DWORD dwNumChars;
int dDirectMode;
if (argc != 2)
{
Syntax();
}
//
// Retrieve the computer name.
//
dwNumChars = MAX_COMPUTERNAME_LENGTH;
if(!GetComputerName(mbsMachineName, &dwNumChars))
{
printf("Failed to get computer name. Exiting...\n");
exit(1);
}
//
// Detect a DS connection and determine the working mode.
//
dDirectMode = SetConnectionMode();
if(strcmp(argv[1], "-s") == 0)
Sender(dDirectMode);
else if (strcmp(argv[1], "-r") == 0)
Receiver(dDirectMode);
else
Syntax();
printf("\nOK\n");
return(0);
}
void CMQTTClient::Run (void)
{
while (1)
{
if (m_ConnectStatus != MQTTStatusDisconnected)
{
Receiver ();
Sender ();
KeepAliveHandler ();
CScheduler::Get ()->MsSleep (50);
}
else
{
CScheduler::Get ()->MsSleep (200);
}
OnLoop ();
}
}
status_t
FDILink::_NormalTrain(uint32 lanes)
{
CALLED();
uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
// Enable normal link training
uint32 tmp = read32(txControl);
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
tmp &= ~FDI_LINK_TRAIN_NONE_IVB;
tmp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
} else {
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
}
write32(txControl, tmp);
tmp = read32(rxControl);
if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
tmp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
tmp |= FDI_LINK_TRAIN_NORMAL_CPT;
} else {
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_NONE;
}
write32(rxControl, tmp | FDI_RX_ENHANCE_FRAME_ENABLE);
// Wait 1x idle pattern
read32(rxControl);
spin(1000);
// Enable ecc on IVB
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
write32(rxControl, read32(rxControl)
| FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
read32(rxControl);
}
return B_OK;
}
void ForwardDecl()
{
/*
ForwardDecl -> PROCEDURE ^ [ Receiver ] identdef [ FormParams ]
*/
if ( debugMode) printf( "In ForwardDecl\n");
accept( PROCEDURE_SYM, 162);
accept( carat, 144);
// first of receiver is (
if ( sym == lparen)
{
Receiver();
}
identdef();
if ( sym == lparen)
{
FormParams();
}
if ( debugMode) printf( "Out ForwardDecl\n");
}
void ProcHead()
{
/*
ProcHead -> PROCEDURE [ Receiver ] identdef [ FormParams ]
*/
if ( debugMode) printf( "In ProcHead\n");
accept( PROCEDURE_SYM, 162);
if ( sym == lparen)
{
// first of receiver
Receiver();
}
identdef();
if ( sym == lparen)
{
// first of FormParams
FormParams();
}
if ( debugMode) printf( "Out ProcHead\n");
}
status_t
FDILink::_AutoTrain(uint32 lanes)
{
CALLED();
uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
uint32 buffer = read32(txControl);
// Clear port width selection and set number of lanes
buffer &= ~(7 << 19);
buffer |= (lanes - 1) << 19;
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB))
buffer &= ~FDI_LINK_TRAIN_NONE_IVB;
else
buffer &= ~FDI_LINK_TRAIN_NONE;
write32(txControl, buffer);
bool trained = false;
for (uint32 i = 0; i < (sizeof(gSnbBFDITrainParam)
/ sizeof(gSnbBFDITrainParam[0])); i++) {
for (int j = 0; j < 2; j++) {
buffer = read32(txControl);
buffer |= FDI_AUTO_TRAINING;
buffer &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
buffer |= gSnbBFDITrainParam[i];
write32(txControl, buffer | FDI_TX_ENABLE);
write32(rxControl, read32(rxControl) | FDI_RX_ENABLE);
spin(5);
buffer = read32(txControl);
if ((buffer & FDI_AUTO_TRAIN_DONE) != 0) {
TRACE("%s: FDI auto train complete!\n", __func__);
trained = true;
break;
}
write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);
write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);
read32(rxControl);
spin(31);
}
// If Trained, we fall out of autotraining
if (trained)
break;
}
if (!trained) {
ERROR("%s: FDI auto train failed!\n", __func__);
return B_ERROR;
}
// Enable ecc on IVB
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
write32(rxControl, read32(rxControl)
| FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
read32(rxControl);
}
return B_OK;
}
status_t
FDILink::_SnbTrain(uint32 lanes)
{
CALLED();
uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
// Train 1
uint32 imrControl = Receiver().Base() + PCH_FDI_RX_IMR;
uint32 tmp = read32(imrControl);
tmp &= ~FDI_RX_SYMBOL_LOCK;
tmp &= ~FDI_RX_BIT_LOCK;
write32(imrControl, tmp);
read32(imrControl);
spin(150);
tmp = read32(txControl);
tmp &= ~FDI_DP_PORT_WIDTH_MASK;
tmp |= FDI_DP_PORT_WIDTH(lanes);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_1;
tmp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
tmp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
write32(txControl, tmp);
write32(Receiver().Base() + PCH_FDI_RX_MISC,
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
tmp = read32(rxControl);
if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
tmp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
tmp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
} else {
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_1;
}
write32(rxControl, rxControl);
Receiver().Enable();
uint32 iirControl = Receiver().Base() + PCH_FDI_RX_IIR;
TRACE("%s: FDI RX IIR Control @ 0x%" B_PRIx32 "\n", __func__, iirControl);
int i = 0;
for (i = 0; i < 4; i++) {
tmp = read32(txControl);
tmp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
tmp |= gSnbBFDITrainParam[i];
write32(txControl, tmp);
read32(txControl);
spin(500);
int retry = 0;
for (retry = 0; retry < 5; retry++) {
tmp = read32(iirControl);
TRACE("%s: FDI RX IIR 0x%" B_PRIx32 "\n", __func__, tmp);
if (tmp & FDI_RX_BIT_LOCK) {
TRACE("%s: FDI train 1 done\n", __func__);
write32(iirControl, tmp | FDI_RX_BIT_LOCK);
break;
}
spin(50);
}
if (retry < 5)
break;
}
if (i == 4) {
ERROR("%s: FDI train 1 failure!\n", __func__);
return B_ERROR;
}
// Train 2
tmp = read32(txControl);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_2;
// if gen6? It's always gen6
tmp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
tmp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
write32(txControl, tmp);
tmp = read32(rxControl);
if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
tmp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
tmp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
} else {
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_2;
}
write32(rxControl, tmp);
read32(rxControl);
spin(150);
for (i = 0; i < 4; i++) {
tmp = read32(txControl);
tmp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
tmp |= gSnbBFDITrainParam[i];
write32(txControl, tmp);
read32(txControl);
spin(500);
int retry = 0;
for (retry = 0; retry < 5; retry++) {
tmp = read32(iirControl);
TRACE("%s: FDI RX IIR 0x%" B_PRIx32 "\n", __func__, tmp);
if (tmp & FDI_RX_SYMBOL_LOCK) {
TRACE("%s: FDI train 2 done\n", __func__);
write32(iirControl, tmp | FDI_RX_SYMBOL_LOCK);
break;
}
spin(50);
}
if (retry < 5)
break;
}
if (i == 4) {
ERROR("%s: FDI train 1 failure!\n", __func__);
return B_ERROR;
}
return B_OK;
}
status_t
FDILink::_IlkTrain(uint32 lanes)
{
CALLED();
uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
// Train 1: unmask FDI RX Interrupt symbol_lock and bit_lock
uint32 tmp = read32(Receiver().Base() + PCH_FDI_RX_IMR);
tmp &= ~FDI_RX_SYMBOL_LOCK;
tmp &= ~FDI_RX_BIT_LOCK;
write32(Receiver().Base() + PCH_FDI_RX_IMR, tmp);
spin(150);
// Enable CPU FDI TX and RX
tmp = read32(txControl);
tmp &= ~FDI_DP_PORT_WIDTH_MASK;
tmp |= FDI_DP_PORT_WIDTH(lanes);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_1;
write32(txControl, tmp);
Transmitter().Enable();
tmp = read32(rxControl);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_1;
write32(rxControl, tmp);
Receiver().Enable();
// ILK Workaround, enable clk after FDI enable
if (fPipeIndex == INTEL_PIPE_B) {
write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);
write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR
| FDI_RX_PHASE_SYNC_POINTER_EN);
} else {
write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);
write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR
| FDI_RX_PHASE_SYNC_POINTER_EN);
}
uint32 iirControl = Receiver().Base() + PCH_FDI_RX_IIR;
TRACE("%s: FDI RX IIR Control @ 0x%" B_PRIx32 "\n", __func__, iirControl);
int tries = 0;
for (tries = 0; tries < 5; tries++) {
tmp = read32(iirControl);
TRACE("%s: FDI RX IIR 0x%" B_PRIx32 "\n", __func__, tmp);
if ((tmp & FDI_RX_BIT_LOCK)) {
TRACE("%s: FDI train 1 done\n", __func__);
write32(iirControl, tmp | FDI_RX_BIT_LOCK);
break;
}
}
if (tries == 5) {
ERROR("%s: FDI train 1 failure!\n", __func__);
return B_ERROR;
}
// Train 2
tmp = read32(txControl);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_2;
write32(txControl, tmp);
tmp = read32(rxControl);
tmp &= ~FDI_LINK_TRAIN_NONE;
tmp |= FDI_LINK_TRAIN_PATTERN_2;
write32(rxControl, tmp);
read32(rxControl);
spin(150);
for (tries = 0; tries < 5; tries++) {
tmp = read32(iirControl);
TRACE("%s: FDI RX IIR 0x%" B_PRIx32 "\n", __func__, tmp);
if (tmp & FDI_RX_SYMBOL_LOCK) {
TRACE("%s: FDI train 2 done\n", __func__);
write32(iirControl, tmp | FDI_RX_SYMBOL_LOCK);
break;
}
}
if (tries == 5) {
ERROR("%s: FDI train 2 failure!\n", __func__);
return B_ERROR;
}
return B_OK;
}
void DeclSeq()
{
/*
DeclSeq -> { CONST { ConstDecl ; }
| TYPE { TypeDecl ; }
| VAR { VarDecl ; } }
{ ProcDecl ; | ForwardDecl ; }
*/
if ( debugMode) printf( "In DeclSeq\n");
while ( sym == CONST_SYM || sym == TYPE_SYM || sym == VAR_SYM)
{
writesym();
switch( sym)
{
case CONST_SYM:
nextsym();
// start of ConstDecl is an ident
while ( sym == ident)
{
ConstDecl();
accept( semic, 151);
}
break;
case TYPE_SYM:
nextsym();
while ( sym == ident)
{
TypeDecl();
accept( semic, 151);
}
break;
case VAR_SYM:
nextsym();
while ( sym == ident)
{
VarDecl();
accept( semic, 151);
}
}
}
while ( sym == PROCEDURE_SYM)
{
writesym();
nextsym();
if ( sym == carat)
{
// then it's ForwardDecl
writesym();
nextsym();
if ( sym != ident)
{
Receiver();
}
identdef();
if ( sym == lparen)
{
FormParams();
}
}
else
{
// it's ProcDecl
if ( sym != ident)
{
Receiver();
}
identdef();
if ( sym == lparen)
{
FormParams();
}
accept( semic, 151);
ProcBody();
accept( ident, 124);
}
accept( semic, 151);
}
if ( debugMode) printf( "Out DeclSeq\n");
}
