PVRSRV_ERROR AwPrePowerState(PVRSRV_DEV_POWER_STATE eNewPowerState, PVRSRV_DEV_POWER_STATE eCurrentPowerState, IMG_BOOL bForced)
{
if(eNewPowerState == PVRSRV_DEV_POWER_STATE_ON)
{
RgxEnableClock();
}
return PVRSRV_OK;
}
IMG_VOID RgxResume(IMG_VOID)
{
RgxEnablePower();
mdelay(2);
/* set external isolation invalid */
sunxi_smc_writel(0, SUNXI_R_PRCM_VBASE + GPU_PWROFF_GATING);
DeAssertGpuResetSignal();
RgxEnableClock();
/* delay for internal power stability */
sunxi_smc_writel(0x100, SUNXI_GPU_CTRL_VBASE + 0x18);
}
PVRSRV_ERROR RgxResume(IMG_VOID)
{
RgxEnablePower();
mdelay(2);
/* set external isolation invalid */
writel(0, SUNXI_R_PRCM_VBASE + GPU_PWROFF_GATING);
RgxEnableClock();
/* wait until gpu pll is stable */
while(!(readl(SUNXI_CCM_PLL_VBASE + 0x9c) & 0x100));
DeAssertGpuResetSignal();
return PVRSRV_OK;
}
PVRSRV_ERROR AwSysPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState)
{
if(eNewPowerState == PVRSRV_SYS_POWER_STATE_ON)
{
RgxEnablePower();
mdelay(2);
/* set external isolation invalid */
writel(0, SUNXI_R_PRCM_VBASE + GPU_PWROFF_GATING);
DeAssertGpuResetSignal();
RgxEnableClock();
/* set delay for internal power stability */
writel(0x100, SUNXI_GPU_CTRL_VBASE + 0x18);
}
return PVRSRV_OK;
}