VOID RtmpDmaEnable(
IN PRTMP_ADAPTER pAd,
IN INT Enable)
{
BOOLEAN value;
ULONG WaitCnt;
WPDMA_GLO_CFG_STRUC GloCfg;
value = Enable > 0 ? 1 : 0;
/* check if DMA is in busy mode or not. */
WaitCnt = 0;
while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
{
RtmpusecDelay(10);
if (WaitCnt++ > 100)
break;
}
RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); /* disable DMA */
GloCfg.field.EnableTxDMA = value;
GloCfg.field.EnableRxDMA = value;
RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); /* abort all TX rings */
RtmpOsMsDelay(5);
return;
}
static INT rtmp_bbp_set_bw(struct _RTMP_ADAPTER *pAd, UINT8 bw)
{
UCHAR val, old_val = 0;
BOOLEAN bstop = FALSE;
UINT32 Data, MTxCycle, macStatus;
if (bw != pAd->CommonCfg.BBPCurrentBW)
bstop = TRUE;
if (bstop)
{
/* Disable MAC Tx/Rx */
RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data);
Data &= (~0x0C);
RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data);
/* Check MAC Tx/Rx idle */
for (MTxCycle = 0; MTxCycle < 10000; MTxCycle++)
{
RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &macStatus);
if (macStatus & 0x3)
RtmpusecDelay(50);
else
break;
}
}
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &old_val);
val = (old_val & (~0x18));
switch (bw)
{
case BW_20:
val &= (~0x18);
break;
case BW_40:
val |= (0x10);
break;
case BW_10:
val |= 0x08;
break;
}
if (val != old_val) {
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, val);
}
if (bstop)
{
/* Enable MAC Tx/Rx */
RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data);
Data |= 0x0C;
RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data);
}
pAd->CommonCfg.BBPCurrentBW = bw;
return TRUE;
}
int mt_rf_read(
RTMP_ADAPTER *ad,
u8 rf_idx,
u16 offset,
u32 *data)
{
u32 i = 0;
u32 value;
int ret;
/* rf control */
RTMP_IO_READ32(ad, RF_CTRL, &value);
/* rf address */
value &= ~RF_ADDR_MASK;
value |= RF_ADDR(offset);
/* read control */
value &= ~RF_R_W_CTRL;
/* rf index */
value &= ~RF_IDX_MASK;
value |= RF_IDX(rf_idx);
RTMP_IO_WRITE32(ad, RF_CTRL, value);
do {
RTMP_IO_READ32(ad, RF_CTRL, &value);
if (RF_READY(value))
break;
i++;
//RtmpOsMsDelay(1);
RtmpusecDelay(50);
//} while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(ad, fRTMP_ADAPTER_NIC_NOT_EXIST)));
} while ((i < MAX_BUSY_COUNT_US) && (!RTMP_TEST_FLAG(ad, fRTMP_ADAPTER_NIC_NOT_EXIST)));
//if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(ad, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
if ((i == MAX_BUSY_COUNT_US) || (RTMP_TEST_FLAG(ad, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n"));
ret = STATUS_UNSUCCESSFUL;
goto done;
}
/* rf data */
RTMP_IO_READ32(ad, R_RFDATA, data);
done:
return ret;
}
/*
========================================================================
Routine Description:
Close kernel threads.
Arguments:
*pAd the raxx interface data pointer
Return Value:
NONE
Note:
========================================================================
*/
VOID RtmpMgmtTaskExit(
IN RTMP_ADAPTER *pAd)
{
INT ret;
RTMP_OS_TASK *pTask;
/* Sleep 50 milliseconds so pending io might finish normally */
RtmpusecDelay(50000);
/* We want to wait until all pending receives and sends to the */
/* device object. We cancel any */
/* irps. Wait until sends and receives have stopped. */
RTUSBCancelPendingIRPs(pAd);
/* We need clear timerQ related structure before exits of the timer thread. */
RtmpTimerQExit(pAd);
/* Terminate cmdQ thread */
pTask = &pAd->cmdQTask;
RTMP_OS_TASK_LEGALITY(pTask)
{
NdisAcquireSpinLock(&pAd->CmdQLock);
pAd->CmdQ.CmdQState = RTMP_TASK_STAT_STOPED;
NdisReleaseSpinLock(&pAd->CmdQLock);
/*RTUSBCMDUp(&pAd->cmdQTask); */
ret = RtmpOSTaskKill(pTask);
if (ret == NDIS_STATUS_FAILURE)
{
/* DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n", */
/* RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev), pTask->taskName)); */
DBGPRINT(RT_DEBUG_ERROR, ("kill command task failed!\n"));
}
pAd->CmdQ.CmdQState = RTMP_TASK_STAT_UNKNOWN;
}
/* Terminate timer thread */
pTask = &pAd->timerTask;
ret = RtmpOSTaskKill(pTask);
if (ret == NDIS_STATUS_FAILURE)
{
/* DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n", */
/* RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev), pTask->taskName)); */
DBGPRINT(RT_DEBUG_ERROR, ("kill timer task failed!\n"));
}
#ifdef WSC_INCLUDED
WscThreadExit(pAd);
#endif /* WSC_INCLUDED */
}
/*
========================================================================
Routine Description:
RTUSB_VendorRequest - Builds a ralink specific request, sends it off to USB endpoint zero and waits for completion
Arguments:
@pAd:
@TransferFlags:
@RequestType: USB message request type value
@Request: USB message request value
@Value: USB message value
@Index: USB message index value
@TransferBuffer: USB data to be sent
@TransferBufferLength: Lengths in bytes of the data to be sent
Context: ! in atomic context
Return Value:
NDIS_STATUS_SUCCESS
NDIS_STATUS_FAILURE
Note:
This function sends a simple control message to endpoint zero
and waits for the message to complete, or CONTROL_TIMEOUT_JIFFIES timeout.
Because it is synchronous transfer, so don't use this function within an atomic context,
otherwise system will hang, do be careful.
TransferBuffer may located in stack region which may not in DMA'able region in some embedded platforms,
so need to copy TransferBuffer to UsbVendorReqBuf allocated by kmalloc to do DMA transfer.
Use UsbVendorReq_semaphore to protect this region which may be accessed by multi task.
Normally, coherent issue is resloved by low-level HC driver, so do not flush this zone by RTUSB_VendorRequest.
========================================================================
*/
NTSTATUS RTUSB_VendorRequest(
IN PRTMP_ADAPTER pAd,
IN UINT32 TransferFlags,
IN UCHAR RequestType,
IN UCHAR Request,
IN USHORT Value,
IN USHORT Index,
IN PVOID TransferBuffer,
IN UINT32 TransferBufferLength)
{
int RET = 0;
POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;
if(in_interrupt())
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("BUG: RTUSB_VendorRequest is called from invalid context\n"));
return NDIS_STATUS_FAILURE;
}
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
{
/*MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("WIFI device has been disconnected\n"));*/
return NDIS_STATUS_FAILURE;
}
else if (RTMP_TEST_PSFLAG(pAd, fRTMP_PS_MCU_SLEEP))
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("MCU has entered sleep mode\n"));
return NDIS_STATUS_FAILURE;
}
else
{
int RetryCount = 0; /* RTUSB_CONTROL_MSG retry counts*/
ASSERT(TransferBufferLength <MAX_PARAM_BUFFER_SIZE);
RTMP_SEM_EVENT_WAIT(&(pAd->UsbVendorReq_semaphore), RET);
if (RET != 0)
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("UsbVendorReq_semaphore get failed! (%d)\n",RET));
return NDIS_STATUS_FAILURE;
}
if ((TransferBufferLength > 0) && ((RequestType == DEVICE_VENDOR_REQUEST_OUT) || (RequestType == DEVICE_CLASS_REQUEST_OUT)))
NdisMoveMemory(pAd->UsbVendorReqBuf, TransferBuffer, TransferBufferLength);
do {
RTUSB_CONTROL_MSG(pObj->pUsb_Dev, 0, Request, RequestType, Value,
Index, pAd->UsbVendorReqBuf, TransferBufferLength,
CONTROL_TIMEOUT_JIFFIES, RET);
if (RET < 0) {
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_OFF, ("#\n"));
if (RET == RTMP_USB_CONTROL_MSG_ENODEV)
{
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST);
break;
}
RetryCount++;
RtmpusecDelay(5000); /* wait for 5ms*/
}
} while((RET < 0) && (RetryCount < MAX_VENDOR_REQ_RETRY_COUNT));
if ( (!(RET < 0)) && (TransferBufferLength > 0) && (RequestType == DEVICE_VENDOR_REQUEST_IN))
NdisMoveMemory(TransferBuffer, pAd->UsbVendorReqBuf, TransferBufferLength);
RTMP_SEM_EVENT_UP(&(pAd->UsbVendorReq_semaphore));
if (RET < 0) {
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("RTUSB_VendorRequest failed(%d),TxFlags=0x%x, ReqType=%s, Req=0x%x, Idx=0x%x,pAd->Flags=0x%lx\n",
RET, TransferFlags, (RequestType == DEVICE_VENDOR_REQUEST_OUT ? "OUT" : "IN"), Request, Index, pAd->Flags));
if (Request == 0x2)
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("\tRequest Value=0x%04x!\n", Value));
if ((!TransferBuffer) && (TransferBufferLength > 0))
hex_dump("Failed TransferBuffer value", TransferBuffer, TransferBufferLength);
if (RET == RTMP_USB_CONTROL_MSG_ENODEV)
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST);
}
}
if (RET < 0)
return NDIS_STATUS_FAILURE;
else
return NDIS_STATUS_SUCCESS;
}
VOID RTMP_BBP_IO_WRITE8(
RTMP_ADAPTER *pAd,
UCHAR bbp_id,
UINT8 Value,
BOOLEAN bViaMCU)
{
BBP_CSR_CFG_STRUC BbpCsr;
int _busyCnt=0, _regID;
BOOLEAN brc;
ULONG __IrqFlags = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT65xx */
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_LOCK(pAd, __IrqFlags);
_regID = (bViaMCU == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG);
for (_busyCnt=1; _busyCnt<MAX_BUSY_COUNT; _busyCnt++)
{
RTMP_IO_READ32((pAd), _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == BUSY)
{
if ( (bViaMCU == TRUE) && ((_busyCnt % 20) == 0))
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
continue;
}
BbpCsr.word = 0;
BbpCsr.field.fRead = 0;
BbpCsr.field.BBP_RW_MODE = 1;
BbpCsr.field.Busy = 1;
BbpCsr.field.Value = Value;
BbpCsr.field.RegNum = bbp_id;
RTMP_IO_WRITE32((pAd), _regID, BbpCsr.word);
if (bViaMCU == TRUE)
{
brc = AsicSendCommandToMcuBBP(pAd, 0x80, 0xff, 0x0, 0x0, FALSE);
if (pAd->OpMode == OPMODE_AP)
RtmpusecDelay(1000);
if (brc == FALSE)
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
pAd->BbpWriteLatch[bbp_id] = Value;
break;
}
if (_busyCnt == MAX_BUSY_COUNT)
{
DBGPRINT_ERR(("BBP write R%d fail\n", bbp_id));
if(bViaMCU == TRUE)
{
RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
BbpCsr.field.Busy = 0;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(pAd, __IrqFlags);
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note:
========================================================================
*/
VOID RTUSBCancelPendingBulkOutIRP(
IN PRTMP_ADAPTER pAd)
{
PHT_TX_CONTEXT pHTTXContext;
PTX_CONTEXT pMLMEContext;
PTX_CONTEXT pNullContext;
PTX_CONTEXT pPsPollContext;
UINT i, Idx;
/* unsigned int IrqFlags;*/
/* NDIS_SPIN_LOCK *pLock;*/
/* BOOLEAN *pPending;*/
/* pLock = &pAd->BulkOutLock[MGMTPIPEIDX];*/
/* pPending = &pAd->BulkOutPending[MGMTPIPEIDX];*/
for (Idx = 0; Idx < 4; Idx++)
{
pHTTXContext = &(pAd->TxContext[Idx]);
if (pHTTXContext->IRPPending == TRUE)
{
/* Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself*/
/* remove it from the HeadPendingSendList and NULL out HeadPendingSendList*/
/* when the last IRP on the list has been cancelled; that's how we exit this loop*/
RTUSB_UNLINK_URB(pHTTXContext->pUrb);
/* Sleep 200 microseconds to give cancellation time to work*/
RtmpusecDelay(200);
}
#ifdef RALINK_ATE
pHTTXContext->bCopySavePad = 0;
pHTTXContext->CurWritePosition = 0;
pHTTXContext->CurWriteRealPos = 0;
pHTTXContext->bCurWriting = FALSE;
pHTTXContext->NextBulkOutPosition = 0;
pHTTXContext->ENextBulkOutPosition = 0;
#endif /* RALINK_ATE */
pAd->BulkOutPending[Idx] = FALSE;
}
/*RTMP_IRQ_LOCK(pLock, IrqFlags);*/
for (i = 0; i < MGMT_RING_SIZE; i++)
{
pMLMEContext = (PTX_CONTEXT)pAd->MgmtRing.Cell[i].AllocVa;
if(pMLMEContext && (pMLMEContext->IRPPending == TRUE))
{
/* Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself*/
/* remove it from the HeadPendingSendList and NULL out HeadPendingSendList*/
/* when the last IRP on the list has been cancelled; that's how we exit this loop*/
RTUSB_UNLINK_URB(pMLMEContext->pUrb);
pMLMEContext->IRPPending = FALSE;
/* Sleep 200 microsecs to give cancellation time to work*/
RtmpusecDelay(200);
}
}
pAd->BulkOutPending[MGMTPIPEIDX] = FALSE;
/*RTMP_IRQ_UNLOCK(pLock, IrqFlags);*/
pNullContext = &(pAd->NullContext);
if (pNullContext->IRPPending == TRUE)
RTUSB_UNLINK_URB(pNullContext->pUrb);
pPsPollContext = &(pAd->PsPollContext);
if (pPsPollContext->IRPPending == TRUE)
RTUSB_UNLINK_URB(pPsPollContext->pUrb);
for (Idx = 0; Idx < 4; Idx++)
{
NdisAcquireSpinLock(&pAd->BulkOutLock[Idx]);
pAd->BulkOutPending[Idx] = FALSE;
NdisReleaseSpinLock(&pAd->BulkOutLock[Idx]);
}
}
VOID RT28xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue = 0;
UINT32 i = 0;
ULONG R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
RTMP_RF_REGS *RFRegTable;
CHAR lan_gain;
#error BOZO
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s(): Can't find the Channel#%d \n", __FUNCTION__, Channel));
}
RFRegTable = RF2850RegTable;
switch (pAd->RfIcType)
{
case RFIC_2820:
case RFIC_2850:
case RFIC_2720:
case RFIC_2750:
for (index = 0; index < NUM_OF_2850_CHNL; index++)
{
if (Channel == RFRegTable[index].Channel)
{
R2 = RFRegTable[index].R2;
if (pAd->Antenna.field.TxPath == 1)
{
R2 |= 0x4000; /*If TXpath is 1, bit 14 = 1;*/
}
if ((pAd->Antenna.field.RxPath == 2)
#ifdef GREENAP_SUPPORT
&& (pAd->ApCfg.bGreenAPActive == FALSE)
#endif /* GREENAP_SUPPORT */
)
{
R2 |= 0x40; /*write 1 to off Rxpath.*/
}
else if ((pAd->Antenna.field.RxPath == 1)
#ifdef GREENAP_SUPPORT
|| (pAd->ApCfg.bGreenAPActive == TRUE)
#endif /* GREENAP_SUPPORT */
)
{
R2 |= 0x20040; /*write 1 to off RxPath*/
}
if (Channel > 14)
{
/* initialize R3, R4*/
R3 = (RFRegTable[index].R3 & 0xffffc1ff);
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15);
/* 5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB*/
/*R3*/
if ((TxPwer >= -7) && (TxPwer < 0))
{
TxPwer = (7+TxPwer);
/* TxPwer is not possible larger than 15 */
R3 |= (TxPwer << 10);
DBGPRINT(RT_DEBUG_TRACE, ("%s(): TxPwer=%d \n", __FUNCTION__, TxPwer));
}
else
{
TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
R3 |= (TxPwer << 10) | (1 << 9);
}
/* R4*/
if ((TxPwer2 >= -7) && (TxPwer2 < 0))
{
TxPwer2 = (7+TxPwer2);
R4 |= (TxPwer2 << 7);
DBGPRINT(RT_DEBUG_TRACE, ("%s(): TxPwer2=%d \n", __FUNCTION__, TxPwer2));
}
else
{
TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
R4 |= (TxPwer2 << 7) | (1 << 6);
}
}
else
{
R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); /* set TX power0*/
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15) | (TxPwer2 <<6);/* Set freq Offset & TxPwr1*/
}
/* Based on BBP current mode before changing RF channel.*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)
#ifdef GREENAP_SUPPORT
&& (pAd->ApCfg.bGreenAPActive == 0)
#endif /* GREENAP_SUPPORT */
)
{
R4 |=0x200000;
}
/* Update variables*/
pAd->LatchRfRegs.Channel = Channel;
pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
pAd->LatchRfRegs.R2 = R2;
pAd->LatchRfRegs.R3 = R3;
pAd->LatchRfRegs.R4 = R4;
/* Set RF value 1's set R3[bit2] = [0]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
RtmpusecDelay(200);
/* Set RF value 2's set R3[bit2] = [1]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
RtmpusecDelay(200);
/* Set RF value 3's set R3[bit2] = [0]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%lu, Pwr1=%lu, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(R3 & 0x00003e00) >> 9,
(R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
break;
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType));
break;
}
/* Change BBP setting during siwtch from a->g, g->a*/
lan_gain = GET_LNA_GAIN(pAd);
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A; /*Gary 2007/08/09 0x050A0A*/
CHAR lan_gain = GET_LNA_GAIN(pAd);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - lan_gain)); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
rtmp_mac_set_band(pAd, BAND_24G);
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
TxPinCfg &= 0xFFFFFFF3;
if (pAd->Antenna.field.RxPath == 1)
TxPinCfg &= 0xFFFFF3FF;
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
filter_coefficient_ctrl(pAd, Channel);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - lan_gain));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0); /*(0x44 - lan_gain)); According the Rory's suggestion to solve the middle range issue. */
/* Set the BBP_R82 value here */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select*/
bbpValue = (pAd->NicConfig2.field.ExternalLNAForA) ? 0x46 : 0x50;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, bbpValue);
/* 5G band selection PIN, bit1 and bit2 are complement*/
rtmp_mac_set_band(pAd, BAND_5G);
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
TxPinCfg &= 0xFFFFFFF3;
if (pAd->Antenna.field.RxPath == 1)
TxPinCfg &= 0xFFFFF3FF;
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds
005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
*/
RtmpusecDelay(1000);
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note:
========================================================================
*/
UCHAR eFuseReadRegisters(PRTMP_ADAPTER pAd, UINT16 Offset, UINT16 Length, UINT16* pData)
{
EFUSE_CTRL_STRUC eFuseCtrlStruc;
INT32 i;
UINT32 efuseDataOffset;
UINT32 data;
UINT32 efuse_ctrl_reg = EFUSE_CTRL;
BOOLEAN IsEmpty = 0;
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
efuse_ctrl_reg = MT_EFUSE_CTRL;
#endif /* MT_MAC */
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
/* Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.*/
/*Use the eeprom logical address and covert to address to block number*/
eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
/* Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 0.*/
eFuseCtrlStruc.field.EFSROM_MODE = 0;
/* Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.*/
eFuseCtrlStruc.field.EFSROM_KICK = 1;
NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
EFUSE_IO_WRITE32(pAd, efuse_ctrl_reg, data);
/* Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.*/
i = 0;
while(i < 500)
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return 0x3f;
/*rtmp.HwMemoryReadDword(EFUSE_CTRL, (DWORD *) &eFuseCtrlStruc, 4);*/
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
{
RtmpusecDelay(2);
break;
}
RtmpusecDelay(2);
i++;
}
/*if EFSROM_AOUT is not found in physical address, write 0xffff*/
if (eFuseCtrlStruc.field.EFSROM_AOUT == 0x3f)
{
for(i = 0; i < Length / 2; i++) {
*(pData +2 * i) = 0xffff;
}
return 0x3f;
} else {
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT) {
if (!eFuseCtrlStruc.field.EFSROM_DOUT_VLD) {
return 0x3f;
}
}
#endif /* MT_MAC */
/*Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x590-0x59C)*/
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
efuseDataOffset = MT_EFUSE_RDATA0 + (Offset & 0xC);
else
#endif /* MT_MAC */
efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC);
/*data hold 4 bytes data.*/
/*In EFUSE_IO_READ32 will automatically execute 32-bytes swapping*/
EFUSE_IO_READ32(pAd, efuseDataOffset, &data);
/*Decide the upper 2 bytes or the bottom 2 bytes.*/
/* Little-endian S | S Big-endian*/
/* addr 3 2 1 0 | 0 1 2 3*/
/* Ori-V D C B A | A B C D*/
/*After swapping*/
/* D C B A | D C B A*/
/*Return 2-bytes*/
/*The return byte statrs from S. Therefore, the little-endian will return BA, the Big-endian will return DC.*/
/*For returning the bottom 2 bytes, the Big-endian should shift right 2-bytes.*/
#ifdef RT_BIG_ENDIAN
data = data << (8*((Offset & 0x3)^0x2));
#else
data = data >> (8*(Offset & 0x3));
#endif /* RT_BIG_ENDIAN */
NdisMoveMemory(pData, &data, Length);
}
return eFuseCtrlStruc.field.EFSROM_AOUT;
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note:
========================================================================
*/
static VOID eFusePhysicalWriteRegisters(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Length,
OUT USHORT* pData)
{
EFUSE_CTRL_STRUC eFuseCtrlStruc;
int i;
UINT32 efuseDataOffset;
UINT32 efuse_rdata = EFUSE_DATA3, efuse_wdata = EFUSE_DATA3;
UINT32 data, eFuseDataBuffer[4];
UINT32 efuse_ctrl_reg = EFUSE_CTRL;
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT) {
efuse_ctrl_reg = MT_EFUSE_CTRL;
efuse_rdata = MT_EFUSE_RDATA0;
efuse_wdata = MT_EFUSE_WDATA0;
}
#endif /* MT_MAC */
/*Step0. Write 16-byte of data to EFUSE_DATA0-3 (0x590-0x59C), where EFUSE_DATA0 is the LSB DW, EFUSE_DATA3 is the MSB DW.*/
/*read current values of 16-byte block */
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
/*Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.*/
eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
/*Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1.*/
eFuseCtrlStruc.field.EFSROM_MODE = 1;
/*Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.*/
eFuseCtrlStruc.field.EFSROM_KICK = 1;
NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
EFUSE_IO_WRITE32(pAd, efuse_ctrl_reg, data);
/*Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.*/
i = 0;
while(i < 500)
{
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
{
RtmpusecDelay(2);
break;
}
RtmpusecDelay(2);
i++;
}
/*Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590)*/
efuseDataOffset = efuse_rdata;
for (i = 0; i < 4; i++)
{
EFUSE_IO_READ32(pAd, efuseDataOffset, (PUINT32) &eFuseDataBuffer[i]);
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
efuseDataOffset += 4;
else
#endif /* MT_MAC */
efuseDataOffset -= 4;
}
/*Update the value, the offset is multiple of 2, length is 2*/
efuseDataOffset = (Offset & 0xc) >> 2;
data = pData[0] & 0xffff;
/*The offset should be 0x***10 or 0x***00*/
if((Offset % 4) != 0)
{
eFuseDataBuffer[efuseDataOffset] = (eFuseDataBuffer[efuseDataOffset] & 0xffff) | (data << 16);
}
else
{
eFuseDataBuffer[efuseDataOffset] = (eFuseDataBuffer[efuseDataOffset] & 0xffff0000) | data;
}
efuseDataOffset = efuse_wdata;
for(i = 0; i < 4; i++)
{
EFUSE_IO_WRITE32(pAd, efuseDataOffset, eFuseDataBuffer[i]);
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
efuseDataOffset += 4;
else
#endif /* MT_MAC */
efuseDataOffset -= 4;
}
/*Step1. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.*/
// TODO: shiang, for below line, windows driver didn't have this read, why we have ??
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
/*Step2. Write EFSROM_MODE (0x580, bit7:bit6) to 3.*/
eFuseCtrlStruc.field.EFSROM_MODE = 3;
/*Step3. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical write procedure.*/
eFuseCtrlStruc.field.EFSROM_KICK = 1;
NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
EFUSE_IO_WRITE32(pAd, efuse_ctrl_reg, data);
/*Step4. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. It's done.*/
i = 0;
while (i < 500)
{
EFUSE_IO_READ32(pAd, efuse_ctrl_reg, &eFuseCtrlStruc.word);
if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
{
RtmpusecDelay(2);
break;
}
RtmpusecDelay(2);
i++;
}
}
VOID EfusePhysicalReadRegisters(PRTMP_ADAPTER pAd, UINT16 Offset,
UINT16 Length, UINT16* pData)
{
EFUSE_CTRL_STRUC EfuseCtrlStruc;
INT32 Index;
UINT32 EfuseDataOffset;
UINT32 Data;
UINT32 EfuseCtrlReg = EFUSE_CTRL;
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
EfuseCtrlReg = MT_EFUSE_CTRL;
#endif /* MT_MAC */
EFUSE_IO_READ32(pAd, EfuseCtrlReg, &EfuseCtrlStruc.word);
/*Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.*/
EfuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
/*Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1.*/
/*Read in physical view*/
EfuseCtrlStruc.field.EFSROM_MODE = 1;
/*Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.*/
EfuseCtrlStruc.field.EFSROM_KICK = 1;
NdisMoveMemory(&Data, &EfuseCtrlStruc, 4);
EFUSE_IO_WRITE32(pAd, EfuseCtrlReg, Data);
/*Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.*/
Index = 0;
while (Index < 500)
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return;
EFUSE_IO_READ32(pAd, EfuseCtrlReg, &EfuseCtrlStruc.word);
if(EfuseCtrlStruc.field.EFSROM_KICK == 0)
{
RtmpusecDelay(2);
break;
}
RtmpusecDelay(2);
Index++;
}
DBGPRINT(RT_DEBUG_INFO, ("EfuseCtrlStruc.field.EFSROM_AOUT = %x\n", EfuseCtrlStruc.field.EFSROM_AOUT));
DBGPRINT(RT_DEBUG_INFO, ("EfuseCtrlStruc.field.EFSROM_DOUT_VLD = %x\n", EfuseCtrlStruc.field.EFSROM_DOUT_VLD));
/*if EFSROM_AOUT is not found in physical address, write 0xffff*/
if (EfuseCtrlStruc.field.EFSROM_AOUT == 0x3f)
{
for(Index = 0; Index < Length / 2; Index++)
{
*(pData + 2 * Index) = 0xffff;
}
DBGPRINT(RT_DEBUG_ERROR, ("EfuseCtrlStruc.field.EFSROM_AOUT = %x\n", EfuseCtrlStruc.field.EFSROM_AOUT));
return;
}
else
{
if (pAd->chipCap.hif_type == HIF_MT)
{
if (!EfuseCtrlStruc.field.EFSROM_DOUT_VLD) {
for(Index = 0; Index < Length / 2; Index++)
{
*(pData + 2 * Index) = 0xffff;
}
DBGPRINT(RT_DEBUG_OFF, ("EfuseCtrlStruc.field.EFSROM_DOUT_VLD = %x\n", EfuseCtrlStruc.field.EFSROM_DOUT_VLD));
return;
}
}
}
/*Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590)*/
/*Because the size of each EFUSE_DATA is 4 Bytes, the size of address of each is 2 bits.*/
/*The previous 2 bits is the EFUSE_DATA number, the last 2 bits is used to decide which bytes*/
/*Decide which EFUSE_DATA to read*/
/*590:F E D C */
/*594:B A 9 8 */
/*598:7 6 5 4*/
/*59C:3 2 1 0*/
#ifdef MT_MAC
if (pAd->chipCap.hif_type == HIF_MT)
EfuseDataOffset = MT_EFUSE_RDATA0 + (Offset & 0xC);
else
#endif /* MT_MAC */
EfuseDataOffset = EFUSE_DATA3 - (Offset & 0xC) ;
EFUSE_IO_READ32(pAd, EfuseDataOffset , &Data);
#ifdef RT_BIG_ENDIAN
Data = Data << (8 *((Offset & 0x3)^0x2));
#else
Data = Data >> (8 * (Offset & 0x3));
#endif /* RT_BIG_ENDIAN */
NdisMoveMemory(pData, &Data, Length);
}
